Integrated circuit for the emission of a voltage which alternate

Details Integrated circuit for the emission of a voltage which alternate Integrated circuit for the emission of a voltage which alternate

1985-07-01

1987-10-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307576, H03K 19096, H03K 513, H03K 17687

Patent

active

047016345

ABSTRACT:
An integrated circuit for emitting a clock voltage V.sub.A which alternates between positive and negative voltage levels with the clock voltage being controllable by means of a unipolar clock voltage V.sub.E and wherein the circuit is a very simple small semiconductor arrangement which has three series connected field effect transistors T1, T2 and T3 with the first end of the series arrangement receiving a first reference voltage and the other end of the series arrangement receiving a second reference voltage. The first and second field effect transistors 1 and 2 or first and second channel types and have gate terminals which are commonly connected to the control input V.sub.E and the junction point 3 of the first two field effect transistors T1 and T2 connected to the output terminal and also connected by way of a capacitor to the gate of the third field effect transistor T3 which is of the first channel type. The gate of the third field effect transistor T3 is connected by way of a diode D or an additional field effect transistor T4 of the first channel type which has its gate connected to the second reference voltage potential.

REFERENCES:
patent: 4122360 (1978-10-01), Kawagai et al.
"CMOS Schmitt Trigger Circuit", IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1985.
RCA Technical Notes, "Improved COS/MOS Inverter Circuit for Reducing Burn-Out and Latch Up", Andrew G. F. Pingwall, Tn No. 1230, pp. 4, Jul. 25, 1979.

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