Integrated circuit for storage and retrieval of multiple digital

Details Integrated circuit for storage and retrieval of multiple digital Integrated circuit for storage and retrieval of multiple digital

1997-06-02

1999-05-18

Nelms, David

Static information storage and retrieval

Floating gate

Multiple values

36518533, G11C11/34

Patent

active

059056738

ABSTRACT:
An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds the multiple bits in a memory cell. Dual banks of shift registers are alternately coupled to one or more data pins and to the memory cells of the memory array speed data transfer for reading and writing operation. Reading is performed in the voltage mode to conserve power. During writing operations, reading of a memory cell is performed in the voltage mode to determine whether the desired programming of the memory cell has been achieved. During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell.

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