Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-02-24
2002-10-08
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185140
Reexamination Certificate
active
06462986
ABSTRACT:
FIELD OF THE INVENTION
This invention-relates in general to semiconductor memories and, in particular, to nonvolatile semiconductor memories with the ability to store multiple digital bits per memory cell.
BACKGROUND OF THE INVENTION
Nonvolatile semiconductor memories, such as EEPROM, EPROM and FLASH integrated circuits, have traditionally been used to store a single digital bit per memory cell. This has been done by changing the threshold voltage (conduction) characteristics of the cell by retaining a certain amount of charge on the floating gate of the memory cell. The threshold voltage range is normally partitioned into two levels (conducting versus nonconducting) to represent the storage of one digital bit per memory cell.
A wide range of charge can be reliably stored on the floating gate to represent a range of threshold voltages. Charge retention on the floating gate can be partitioned to represent multiple number of threshold voltage ranges and the threshold range can be partitioned into multiple ranges to represent storage of more than one bit of digital data per memory cell. For example, four threshold partitions can be used to represent storage of two digital bits per memory location and sixteen partitions to represent storage of four digital bits per memory location. Furthermore, the threshold voltage range can be partitioned to appropriately finer resolution to represent the direct storage of analog information per memory cell.
The ability to store multiple digital bits per memory cell increases the effective storage density per unit area and reduces the cost of storage per digital bit. In addition to this, in the field of semiconductor memories, the costs of a-modern fabrication facility often exceeds a billion dollars. Application of multibit storage per cell techniques to existing memory fabrication processes and facilities allows the production of the next generation of higher density storage devices in the same manufacturing facilities, thereby increasing profitability and the return on investment.
Nonetheless, the problem of operational speed, i.e., the reading and writing operations, have yet to be satisfactorily addressed for devices having multiple bits per memory cell. A related problem is power dissipation. As more power is used to increase operational speeds, power consumption is also undesirably increased. Still another problem is reliability. While charges can be stored in the floating gates of memory cells for very long periods, erasing and rewriting charges causes long term problems as to the certainty of the bits stored in a memory cell. And, of course, any integrated circuit has problems of space. In an integrated circuit having multiple bits per cell, additional circuits must be added to handle the new requirements. This partially negates the advantages of the increased bits per memory cell.
The present invention solves or substantially mitigates these problems. The present invention speeds up the reading and writing operations of multibit memory cells. Power dissipation is lowered for reading operations. The present invention also permits the reliable determination of the bits in the memory cells over the long term and also conserves space on the integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides for an integrated circuit having an array of memory cells, each memory cell storing multiple bits of information, end at least one data terminal. The integrated circuit also has a plurality of latches connected to the array of memory cells with the latches organized into a first bank and a second bank. For reading and writing operations from and into the memory cell array, the latches and memory cell array are controlled so the first bank is coupled to the array of memory cells while the second bank is coupled to the data terminal. Alternately the second bank to the array of memory cells while first bank is coupled to said one data terminal. This alternate coupling permits data to be simultaneously transferred between one bank of latches and the array of memory cells and transferred between another bank of latches and the data terminal for faster read and write operations.
To lower power dissipation, the memory cells of the array are read by voltage-mode operation. Furthermore, during writing operations, a voltage corresponding to the amount of charge stored in the selected memory cell is compared to a reference voltage to determine whether high voltage programming of the memory cell should continue. Programming of the memory cells is terminated when the corresponding voltage matches the reference voltages.
For reading operations, the voltage corresponding to the amount of charge stored in a selected memory cell is compared to a sequence of reference voltages in a binary search pattern to determine the plurality of bits stored in the memory cell.
REFERENCES:
patent: 4054864 (1977-10-01), Audaire et al.
patent: 4181980 (1980-01-01), McCoy
patent: 4415992 (1983-11-01), Adldoch
patent: 4448400 (1984-05-01), Harari
patent: 4612629 (1986-09-01), Harari
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4627027 (1986-12-01), Rai et al.
patent: 4667217 (1987-05-01), Janning
patent: 4771404 (1988-09-01), Mano et al.
patent: 4794565 (1988-12-01), Wu et al.
patent: 4890259 (1989-12-01), Simko
patent: 4989179 (1991-01-01), Simko
patent: 5029130 (1991-07-01), Yeh
patent: 5042009 (1991-08-01), Kazerounian et al.
patent: 5043940 (1991-08-01), Harari
patent: 5119330 (1992-06-01), Tanagawa
patent: 5150327 (1992-09-01), Matsushima et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5198380 (1993-03-01), Harari
patent: 5218569 (1993-06-01), Banks
patent: 5218571 (1993-06-01), Norris
patent: 5220531 (1993-06-01), Blyth et al.
patent: 5222047 (1993-06-01), Matsuda et al.
patent: 5241494 (1993-08-01), Blyth et al.
patent: 5243239 (1993-09-01), Khan et al.
patent: 5258759 (1993-11-01), Cauwenberghs et al.
patent: 5258949 (1993-11-01), Chang et al.
patent: 5268870 (1993-12-01), Harari
patent: 5283761 (1994-02-01), Gillingham
patent: 5293560 (1994-03-01), Harari
patent: 5294819 (1994-03-01), Simko
patent: 5297096 (1994-03-01), Terada et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5336936 (1994-08-01), Allen et al.
patent: 5352934 (1994-10-01), Khan
patent: 5357476 (1994-10-01), Kuo et al.
patent: 5365486 (1994-11-01), Schreck
patent: 5371031 (1994-12-01), Gill et al.
patent: 5388064 (1995-02-01), Khan
patent: 5394362 (1995-02-01), Bank
patent: 5412601 (1995-05-01), Sawada et al.
patent: 5422842 (1995-06-01), Cernea et al.
patent: 5440505 (1995-08-01), Fazio et al.
patent: 5440518 (1995-08-01), Hazani
patent: 5475634 (1995-12-01), Wang et al.
patent: 5477499 (1995-12-01), Van Buskirk et al.
patent: 5479170 (1995-12-01), Cauwenberghs et al.
patent: 5485422 (1996-01-01), Bauer et al.
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5508958 (1996-04-01), Fazio et al.
patent: 5511020 (1996-04-01), Hu et al.
patent: 5521865 (1996-05-01), Ohuchi et al.
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5539688 (1996-07-01), Yiu et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5546341 (1996-08-01), Suh et al.
patent: 5555519 (1996-09-01), Takashima et al.
patent: 5566111 (1996-10-01), Choi
patent: 5566125 (1996-10-01), Fazio et al.
patent: 5590076 (1996-12-01), Haddad et al.
patent: 5592415 (1997-01-01), Kato et al.
patent: 5615159 (1997-03-01), Roohparvar
patent: 5615163 (1997-03-01), Sakui et al.
patent: 5627784 (1997-05-01), Roohparvar
patent: 5629890 (1997-05-01), Engh
patent: 5633822 (1997-05-01), Campardo et al.
patent: 5652450 (1997-07-01), Hirano
patent: 5657332 (1997-08-01), Auclair et al.
patent: 5663923 (1997-09-01), Baltar et al.
patent: 5671176 (1997-09-01), Jang et al.
patent: 5677885 (1997-10-01), Roohparvar
patent: 5687114 (1997-11-01), Khan
patent: 5694356 (1997-12-01), Wong et al.
patent: 5708620 (1998-01-01), Jeong
patent: 5712815 (1998-01-01), Bill et al.
patent: 5761109 (1998-06-01), Takashina et al.
patent: 5761117 (1998-06-01), Uchino et al.
patent: 576
Elms Richard
Gray Cary Ware & Freidenrich LLP
Nguyen Hien
Silicon Storage Technology, Inc.
LandOfFree
Integrated circuit for storage and retrieval of multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit for storage and retrieval of multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit for storage and retrieval of multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2928907