Pulse or digital communications – Receivers – Automatic baseline or threshold adjustment
Reexamination Certificate
1999-08-11
2002-08-20
Pham, Chi (Department: 2631)
Pulse or digital communications
Receivers
Automatic baseline or threshold adjustment
C375S354000, C327S307000
Reexamination Certificate
active
06438178
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an integrated circuit for receiving and recovering a digital data bit stream which has been transmitted over a communication channel, such as a 140-155 Mbit/s Code Mark Inversion (CMI) digital data bit stream transmitted over communication channels operating according to E4/STM-1/OC-3 protocols. The integrated circuit may comprise a cable equaliser circuit, a Loss of Signal (LOS) detection circuit and a Clock and Data Recovery circuit to provide a single-chip interface solution for reception of high speed digital data bit streams.
The present invention also relates to a LOS detection circuit which is capable of accurately detecting a presence or absence of the incoming electrical signal by monitoring a level of the received digital data bit stream on a bit by bit basis and compare the level of each of the received data bits to a predetermined threshold value or values. The present LOS detection circuit may furthermore be adapted to comply with LOS defect specifications defined by the ITU-T G. 703 standard for 140-155 Mbit/s system bit rates by counting a number of data bit periods of the digital data bit stream and detect how many of those data bit periods that contained signal levels larger than an upper threshold value and/or smaller than a lower threshold value.
BACKGROUND OF THE INVENTION
In high speed digital communication systems, it is important to be able to rapidly and reliably determine the loss of a incoming electrical signal transmitted to a receiver circuit over the communication channel of a communication system. Accordingly, receiver chip sets or chips are often provided with circuitry which is adapted to monitor a signal level of the incoming electrical signal of the digital data bit stream or data stream to determine whether the data stream is present or not and provide a LOS defect signal indicating whether the data stream is present or absent. Often, this LOS defect signal is transferred to a system processor or network controller, i.e. Personal Computer or workstation running a suitable monitoring program, monitoring the operation of the communication system, which may be adapted to e.g. shut down the system in response to an activated LOS defect signal.
Accordingly, although the receiver chip must respond rapidly to a true loss event, it must not activate the LOS defect signal in response to minor LOS events constituted by allowed variations or fluctuations in the level of incoming electrical signal or by short duration random noise pulses or bursts. Allowed variations in the received signal level are often defined in technical standards, such as ITU-T G.775 that defines a number of criteria for activation and clearance of the LOS defect signal based on the level of the incoming electrical signal. Avoiding unintended shutdowns due to the previously mentioned minor LOS events require very precise control of a level detector's threshold value or values in the LOS detector circuit. Furthermore, a LOS detector operating according to ITU-T G.775 should also be capable of determining and counting for how many data bit periods, of a recovered data stream the incoming electrical signal level is below or above the threshold value(s). By providing a such count value and basing a decision as to whether the incoming electrical signal is present or not, i.e. whether the LOS defect signal should be activated or cleared, it may be avoided that the LOS circuit reacts instantaneously to the above-mentioned minor LOS events. Instead well-defined criteria in terms of a threshold value(s) of the level of the incoming electrical signal and the duration, counted in data bit periods, of such minor LOS events can be provided and utilised as a decision basis for a network controller controlling a state of the LOS defect signal.
Many known LOS detection circuits use a peak detector to convert an incoming AC signal of a data stream to a e.g. proportional DC value which can be compared to a predetermined threshold voltage to determine when the incoming AC signal level has fallen below a predetermined threshold value. Examples of circuits operating according to such principles are known from U.S. Pat. No. 4,795,919 and GB 2 301 723. The peak detectors disclosed in those references use integrated transistors, diodes and resistors, but usually external capacitors to generate the required DC signal that represents the peak value of the incoming signal. There are several drawback associated with this level detecting methodology. The external capacitor which provides the required DC value of the incoming signal also introduces some uncertainty to the time constants of the detector circuit due to an inherent tolerance on the capacitor's value and its lack of tracking with inherent variations in integrated component's resistance and transconductance values. For high speed data signal, such as data rates above 140 Mbit/s, parasitic capacitance and inductance associated with the integrated circuit's (IC's) package and bonding wires makes the resulting time constant of such partly internal and partly external peak detecting circuit even less well defined. EP 0 667 533 discloses a LOS detector circuit for detecting LOS events of an incoming signal. The LOS detector circuit comprise a pair of comparators that compare a level of an incoming signal to predetermined threshold voltages to determine if the signal level is within a predetermined voltage range defined by the threshold voltages. Comparator output signals are processed and transferred to a “smearing circuit” that combines the input signal of the smearing circuit with successively delayed versions of the same signal in an AND gate. Accordingly, only LOS events of incoming signals that have a duration longer than the total delay path are detected as true minor LOS events at the output of the smearing circuit. The delay time of the delay path is adjusted to be equivalent to about one data bit period of the incoming signal to avoid short noise burst or similar short time signal corruption to trigger or activate a LOS defect signal. This LOS detector circuit is not capable of reliably detecting incoming electrical signals wherein the signal level is sufficiently low to only rise above the thresholds voltage(s) in short time periods, a situation often encountered during reception of electrical signals which have been transmitted over an electrical cable, since such signals are attenuated and have a substantially triangular waveform shape. Furthermore, the required adjustment of the delay time of the delay path to match each data bit rate that needs to be supported and the very poor control over the absolute delay time of inverter elements on integrated circuits are both impractical.
SUMMARY OF THE INVENTION
It is an object of one embodiment of the invention to provide a single integrated circuit that comprises a cable equaliser circuit, a LOS detection circuit and a CDR circuit to obtain a single chip solution for receiving and retrieving an incoming electrical signal of a data stream and for controlling a state of the LOS defect signal in accordance with predetermined criteria as to the required signal level of the incoming electrical signal and to the duration of LOS events in the electrical signal. is also an object of the invention to provide a LOS detection circuit that may be adapted to comply with the ITU-T G.775 specification for generation of LOS defect signals.
It is further an object of the invention to provide a LOS detection circuit that is capable of reliably detecting the presence or absence of a low level electrical signal comprising data bits with a substantially triangular signal wave shape due to the transmission over an electrical cable based communication channel.
It is further an object of the invention to provide a LOS detection circuit capable of comparing the level of consecutive data bits within the received data stream on a bit by bit basis to a predetermined threshold voltage(s).
It is further an object of the invention to provide a LOS
Johansen Henrik Ingvar
Liere Michael
Lysdal Henning
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Pham Chi
Phu Phuong
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