Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2000-03-06
2001-10-23
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S239000
Reexamination Certificate
active
06307416
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated circuit for producing two output clock signals, in which first logic levels of the output clock signals do not overlap in time.
Such circuits are required, for example, for actuating shift registers, in which a plurality of register elements are arranged in a series circuit, and are connected to one another via switching elements. It is thereby important that the switching element on the input side and the switching element on the output side of one of the register elements are not both switched on at any time. It is thus advantageous for the two switching elements each to be actuated by different clocks, the switching element being switched on at a first clock signal logic level, and being switched off at the other logic level. In order to avoid both switching elements from being switched on at the same time, it is essential that the first logic levels of the two clock signals do not overlap in time.
SUMMARY OF THE INVENTION
The object of the invention is to provide an integrated circuit for producing two output clock signals which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which provides for first logic levels which do not overlap in time. Furthermore, the time interval during which neither of the output clock signals is at the first logic level should be as short as possible.
With the above and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
a first input and a second input each supplying one input clock;
a first output outputting a first output clock signal and a second output outputting a second output clock signal, the output clock signals having first logic levels that do not overlap in time;
a first and a second inverter connected back to back and between the first and second outputs;
a first series circuit comprising a first switching element having a control connection connected to the first input and a second switching element having a control connection, the first series circuit connecting the first output to a supply potential;
a second series circuit comprising a third switching element having a control connection connected to the second input and a fourth switching element having a control connection, the second series circuit connecting the second output to the supply potential;
a first circuit unit connected to the control connection of the second switching element, the first circuit unit, during an operation of the circuit, supplying the second switching element with a signal derived from the input clock supplied to the first input; and
a second circuit unit connected to the control connection of the fourth switching element, the second circuit unit, during an operation of the circuit, supplying the second switching element with a signal derived from the input clock supplied to the second input.
The invention allows the generation of the two output clock signals, whose first logic levels do not overlap in time, from two input clocks whose logic levels may overlap in any way in time.
In accordance with an added feature of the invention, a third and a fourth inverter are connected back to back (anti-parallel) and between the control connections of the second and the fourth switching element; and further,
the first circuit unit has a third series circuit comprising a fifth switching element with a control connection connected to the second output and a sixth switching element with a control connection, the third series circuit connecting the control connection of the second switching element to the supply potential;
the second circuit unit has a fourth series circuit comprising a seventh switching element with a control connection connected to the first output and an eighth switching element with a control connection, the fourth series circuit connecting the control connection of the fourth switching element to the supply potential;
a fifth inverter is connected between the second input and the control connection of the sixth switching element; and
a sixth inverter is connected between the first input and the control connection of the eighth switching element.
In accordance with an additional feature of the invention:
the first circuit unit includes a first inverting delay element and the second circuit unit includes a second inverting delay element;
the first inverting delay element connecting the first input to the control connection of the second switching element; and
the second inverting delay element connecting the second input to the control connection of the fourth switching element.
In accordance with another feature of the invention, a delay unit is connected to each of the first and second outputs for producing a different delay for the two edge types of the respective output clock. In this way, it is advantageously possible to minimize the time interval during which neither of the output clock signals is at the first logic level.
In accordance with a further feature of the invention:
the delay units include first and second capacitors, respectively, with a capacitance depending on a polarity of a voltage drop across the respective capacitor;
the first output is connected via the first capacitor to the control connection of the second switching element; and
the second output is connected via the second capacitor to the control connection of the fourth switching element.
In accordance with again a further feature of the invention, the delay units each include an inverter having an input connected to a corresponding one of the outputs and producing a different delay for the two edge types.
In accordance with a concomitant feature of the invention:
the first output is connected via the second switching element to the first switching element; and
the second output is connected via the fourth switching element to the third switching element.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit for producing two output clock signals at levels which do not overlap in time, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5173618 (1992-12-01), Eisenstadt
patent: 5874845 (1999-02-01), Hynes
patent: 2186455A (1987-08-01), None
Graetz Thoralf
Harle Dieter
Heyne Patrick
Cox Cassandra
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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