Integrated circuit for pipeline data processing

Details Integrated circuit for pipeline data processing Integrated circuit for pipeline data processing

1993-10-21

1996-11-05

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 364271, 3642714, 3642715, 395376, G06F 112

Patent

active

055727140

ABSTRACT:
The present invention discloses an integrated circuit for use in pipeline processing formed by a plurality of stages. Data is latched by a first latch. A first logic element receives the output of the first latch and processes it. A second latch receives the output of the first logic element and processes it. A second logic element receives the output of the second latch and processes it. If the processing time of the first logic element is longer than that of the second logic element, a clock signal being applied to the second latch which gives its output to the second logic element is delayed by a delay element a given delay time. Such a given delay time is determined to be below the minimum delay time of the first logic element. Cycles per pipeline stage are variable. With a clock cycle shorter than the processing time of one of the first and second logic elements that has a longer processing time than the other, pipeline processing becomes possible. Therefore, data processing time shortens.

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