Integrated circuit for network stress testing

Details Integrated circuit for network stress testing Integrated circuit for network stress testing

2005-01-07

2011-10-11

Jain, Raj (Department: 2472)

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

C370S230000, C370S231000

Reexamination Certificate

active

08036123

ABSTRACT:
An integrated circuit having a corresponding method comprises a plurality of ports to transmit and receive packets of data; a forwarding engine to transfer the packets of data between the ports; and a controller to receive one or more packet definitions that specify characteristics of a packet; and wherein at least one of the ports comprises a packet generator to originate one or more packets of data according to one or more of the packet definitions received by the controller.

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U.S. Patent Application No. (To Be Assigned), filed Jan. 7, 2005, entitiled, “Integrated Circuit for Network Delay and Jitter Testing”.
IEEE P802.1ag/D0.0, Draft Standard for Local and Metropolitan Area Networks, Virtual Bridged Local Area Networks—Amendment 5: Connectivity Fault Management; May 6, 2004, 72 pages.

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