Integrated circuit for generating a reset signal

Details Integrated circuit for generating a reset signal Integrated circuit for generating a reset signal

1992-01-22

1992-11-24

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072723, 307350, 307363, G11C 1100, H03K 301

Patent

active

051665468

ABSTRACT:
An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.

REFERENCES:
patent: 4210829 (1980-07-01), Wong et al.
patent: 4902907 (1990-02-01), Haga et al.
patent: 4948995 (1990-08-01), Takahashi
patent: 5027006 (1991-06-01), Queinnec et al.
Toute l'Electronique, No. 454, May 1980, Paris, pp. 91-94 "Triggers de Schmitt C-MOS".
Electronic Design, vol. 34, No. 9, Apr. 1986, N.J., pp. 77,78,80,82,84 (Bernhard).
Research Disclosure, May 1987, No. 277, New York, p. 317, "CMOS On-Chip VDD Lock-Pulse".

Affiliated with

Also associated with

Rating

Integrated circuit for generating a reset signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit for generating a reset signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit for generating a reset signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-924090