Integrated circuit for generating a plurality of direct...

Details Integrated circuit for generating a plurality of direct... Integrated circuit for generating a plurality of direct...

2006-04-04

2006-04-04

Sircus, Brian (Department: 2836)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S267000, C323S901000

Reexamination Certificate

active

07023187

ABSTRACT:
A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.

REFERENCES:
patent: 2929924 (1960-03-01), Miller
patent: 4313155 (1982-01-01), Bock et al.
patent: 4361865 (1982-11-01), Shono
patent: 4504898 (1985-03-01), Pilukaitis et al.
patent: 4628426 (1986-12-01), Steigerwald
patent: 4887199 (1989-12-01), Whittle
patent: 4935858 (1990-06-01), Panicali
patent: 5267135 (1993-11-01), Tezuka et al.
patent: 5307004 (1994-04-01), Carsten
patent: 5400239 (1995-03-01), Caine
patent: 5455501 (1995-10-01), Massie
patent: 5715153 (1998-02-01), Lu
patent: 5861737 (1999-01-01), Goerke et al.
patent: 5886508 (1999-03-01), Jutras
patent: 5903138 (1999-05-01), Hwang et al.
patent: 5991168 (1999-11-01), Farrington et al.
patent: 6067241 (2000-05-01), Lu
patent: 6087817 (2000-07-01), Varga
patent: 6195275 (2001-02-01), Lu
patent: 6198642 (2001-03-01), Kociecki
patent: 6222352 (2001-04-01), Lenk
patent: 6297976 (2001-10-01), Isono
patent: 6430070 (2002-08-01), Shi et al.
patent: 6469478 (2002-10-01), Curtin
patent: 6515880 (2003-02-01), Evans et al.
patent: 6611436 (2003-08-01), Nishida et al.
patent: 6756772 (2004-06-01), McGinnis
patent: 6771052 (2004-08-01), Ostojic
patent: 6813170 (2004-11-01), Yang
patent: 6838861 (2005-01-01), Testin
Lokhandwala, Adnan M. and Sudip K. Mazumder. “Discrete Validation of Smart Power ASIC (SPIC) for a Distributed Power System”. 2004 35th Annual IEEE Power Electronics Specialists Conference.
U.S. Appl. No. 09/442,299, entitled: Active Decoupling and Power Management Circuit for Line-Powered Ringing Generator.
U.S. Appl. No. 09/378,382, entitled: Power-Limited Remote Termination Converter with Wetting Current and Emergency Power Operation for Digital Data Services Equipment.

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