Pulse or digital communications – Receivers
Reexamination Certificate
2001-12-24
2004-01-06
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
C455S161300
Reexamination Certificate
active
06674813
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The invention relates to an integrated circuit for detecting a received signal, which can be used, for example, in radio receivers and in particular in mobile radio receivers, as well as a circuit configuration with an integrated circuit.
Voltage-controlled oscillators (VCO) which are tuned with a phase locked loop (PLL) have become established in radio reception technology. The oscillator frequency of the voltage-controlled oscillator is tuned using the phase locked loop with a specific step size, for example with a frequency step size of 100 KHz in frequency-modulated radio in Europe. During the transmitter search run, the entire FM band (87.5 MHz to 108 MHz) is preferably scanned in 100 KHz increments. The oscillator frequency of the voltage-controlled oscillator fOSC is typically 10.7 MHz above the input frequency to be received, that is to say between 98.2 MHz and 118.7 MHz.
During the transmitter search run, as far as possible all the transmitters which are worth receiving are to be found and their input frequency or the corresponding oscillator frequency fOSC of the voltage-controlled oscillator are to be stored. If a transmitter is detected at any particular reception frequency, the phase locked loop is stopped at the a instantaneous value by the microcontroller. The corresponding values are stored in the microcontroller so that these transmitter stations which are determined can be set directly at a later time. In order to be able to detect the transmission stations, one or—for sake of increased detection precision—a plurality of criteria are required in order to stop the voltage-controlled oscillator at the corresponding oscillator frequency. It is therefore necessary to use one, or preferably a plurality of, evaluation criteria in the receiver in order to to detect unambiguously the presence of an input signal which is worth receiving.
In order to increase the reliability with which a transmitter can be detected unambiguously, it is possible to use not only the field-strength signal (level of the received signal) but also the multipath signal which indicates whether the received signal is scattered by multipath reception. To do this, the field-strength signal and the multipath signal are fed to a microprocessor which digitizes these signals and evaluates them through the use of criteria which are predefined in the microprocessor. Finally, in the microprocessor it is decided whether the transmitter is one which is worth receiving. The disadvantage of such a circuit configuration is that a plurality of lines are required from the receiver module to the microprocessor and unavoidable data traffic occurs on the data bus during the transmitter search run. However, this not only unnecessarily severely loads the microprocessor but the data traffic also constitutes a permanent source of interference in the sensitive reception system. In order to keep the data traffic as low as possible, the transmitter search criterion of intermediate frequency counting is therefore frequently not included, which however has the disadvantage of less precise transmitter identification. In many cases, for a more reliable search run stop it is not sufficient to evaluate only one of the search run stop criteria including the field-strength signal, multipath signal, zero crossover of the S curve and the limited intermediate frequency transmitted from the input mixer to the intermediate frequency amplifier. It is difficult to reliably detect weakly receivable transmitters only through the use of the field-strength.
European Patent Application No. EP 0 430 469 A2 discloses a circuit for detecting a received signal for FM receivers. The detector contains an intermediate frequency detector, a field-strength comparator and a noise signal detector whose output signals are combined with one another in a logic switching element to form a signal path. A microprocessor is driven as a function of this.
Patent Abstracts of Japan, Volume 009, No. 248 (E-347), Oct. 4, 1985 (JP-A-60-096913) discloses how to use a noise detector to detect noise on the basis of multipath signals.
European Patent Application No. EP 0 335 141 A2 discloses a configuration for detecting various reception characteristic variables including a multipath reception, the outputs of which are coupled to a logic element.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit for detecting a received signal which overcomes the above-mentioned disadvantages of the heretofore-known circuits of this general type and which permits a transmitter identification as quickly and reliably as possible while avoiding interference.
With the foregoing and other objects in view there is provided, in accordance with the invention, in combination with a microprocessor, an integrated circuit for detecting a received signal, including:
an intermediate frequency detector configured to detect an intermediate frequency and supplying a first search run stop signal if the intermediate frequency is within a given range;
a field-strength comparator configured to supply a second search run stop signal if a field-strength of the received signal exceeds a field-strength setpoint value;
a multipath comparator configured to supply a third search run stop signal if a multipath signal exceeds a given multipath setpoint valve;
a logic component operatively connected to the intermediate frequency detector, the field-strength comparator, and the multipath comparator, the logic component logically combining the first, second and third search run stop signals with one another and forming a binary stop signal, the logic component having an output and providing the binary stop signal as a statically present signal at the output of the logic component, and the microprocessor receiving, as an input signal, the binary stop signal provided at the output of the logic component;
a first analog/digital converter connected upstream of the field-strength comparator, the first analog/digital converter digitizing a field-strength signal;
a first serial/parallel converter connected between the first analog/digital converter and the field-strength comparator;
a second analog/digital converter connected upstream of the multipath comparator, the second analog/digital converter digitizing the multipath signal; and
a second serial/parallel converter connected between the second analog/digital converter and the multipath comparator.
In other words, the integrated circuit according to the invention for detecting a received signal has an intermediate frequency detector which supplies a first search run stop signal if the intermediate frequency lies within a specific range. Furthermore, the integrated circuit has a field-strength comparator which supplies a second search run stop signal if the field-strength of the received signal exceeds a field-strength setpoint value. The invention additionally has a multipath comparator which supplies a third search run stop signal if the multipath signal exceeds a specific multipath setpoint value. Furthermore, a logic component is provided which logically combines the three search run stop signals with one another to form a binary stop signal which is statically present at the output of the logic component and is made available to a microprocessor as its input signal.
The data traffic between the microprocessor and the integrated circuit is reduced, which results in a severe reduction in interference.
The integrated circuit has the advantage that the overall space required for the radio receiver can be reduced as a result of the integration of a first analog/digital converter, which is connected upstream of the field-strength comparator and serves to digitize the field-strength signal, into the integrated circuit. Likewise, the external electrical lines, which therefore run outside the integrated circuit, can therefore be reduced, which also reduces the susceptibility to interference.
A second analog/digital converter which is connected upstream of the multipa
Kröbel Hans-Eberhard
Stepp Richard
Chin Stephen
Greenberg Laurence A.
Infineon - Technologies AG
Kim Kevin
Locher Ralph E.
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