Patent
1976-09-13
1978-05-09
Griffin, Robert L.
H04B 116
Patent
active
040889580
ABSTRACT:
An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation.
REFERENCES:
patent: 3800230 (1974-03-01), Marks et al.
patent: 3818352 (1974-06-01), Moran
patent: 4004085 (1977-01-01), Makino et al.
"Electronics," vol. 47, No. 1, Jan. 10, 1974, pp. 36-37.
"Electronics," vol. 48, No. 24, Nov. 1975, pp. 5E-6E.
"Funkschau," vol. 47, No. 16, Aug. 1975, pp. 37-38.
Kokado Nawoyuki
Kudo Yukinori
Shigematsu Tomohisa
Suzuki Yasoji
Bookbinder Marc E.
Griffin Robert L.
Tokyo Shibaura Electric Co. Ltd.
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