Integrated circuit featuring a non-volatile memory with...

Details Integrated circuit featuring a non-volatile memory with... Integrated circuit featuring a non-volatile memory with...

2007-05-31

2009-06-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185140, C365S185230, C365S185260, C365S185290, C365S185310

Reexamination Certificate

active

07542351

ABSTRACT:
An integrated circuit (10) comprises a plurality of non-volatile memory cells (14) and a charge distribution ramp rate control circuit (11). Each memory cell of the array (12) includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor (62,116,144) having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source (58,106,136) for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.

REFERENCES:
patent: 5365121 (1994-11-01), Morton et al.
patent: 5687116 (1997-11-01), Kowshik et al.
patent: 5872733 (1999-02-01), Buti et al.
patent: 7151695 (2006-12-01), Choy et al.
patent: 2003/0122617 (2003-07-01), Johnston
patent: 2006/0104121 (2006-05-01), Choy et al.
patent: 2007/0121382 (2007-05-01), Chan et al.

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