Integrated circuit fast multiplier structure

Details Integrated circuit fast multiplier structure Integrated circuit fast multiplier structure

1983-03-18

1986-02-18

Thomas, James D.

Boots, shoes, and leggings

G06F 752

Patent

active

045717010

ABSTRACT:
There is disclosed a multiplier structure including elementary multipliers and a matrix of binary adder cells of the high-speed carry propagation type associated with the elementary multipliers. The intermediate results to be added are transferred along a matrix diagonal from each adder cell to an adder cell p lines and p columns distant therefrom, where p is a whole number greater than one. The matrix of binary adder cells does not contain cells associated with the first p lines and columns of elementary multipliers and is supplemented by p-1 columns or lines of additional cells on the output side of the matrix furnishing the least significant bits and by p lines or columns of additional cells on the output side of the matrix furnishing the most significant bits. The additional adder cells serve to gather the intermediate results furnished by the adder cells of the p adjacent columns and lines of the associated matrix in order to produce the bits of the final product. The sum signal generation time is approximately p times greater than their carry propagation time to reestablish the balance in the multiplier structure between the sum and carry propagation times so as to maximize the advantage of improved carry propagation speed in the binary adder cells.

REFERENCES:
patent: 3346729 (1967-10-01), Dell et al.
patent: 4441158 (1984-04-01), Kanuma

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