Fishing – trapping – and vermin destroying
Patent
1993-11-05
1995-08-08
Quach, T. N.
Fishing, trapping, and vermin destroying
437228, H01L 21283, H01L 21316
Patent
active
054398479
ABSTRACT:
A method for etching metal conductors and stacks of conductors is disclosed. A doped silicon dioxide layer is deposited upon a metal or stack of conductive layers to be etched. A silicon dioxide layer is doped with phosphorous. Next, the silicon dioxide layer is partially etched and the photoresist removed. Subsequent etching utilizes the raised feature created in the silicon dioxide layer as a mask to etch the underlying metal or stack of conductors.
REFERENCES:
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 4676869 (1987-06-01), Lee et al.
patent: 4728617 (1988-03-01), Woo et al.
patent: 4786609 (1988-11-01), Chen
patent: 4820611 (1989-04-01), Arnold, III et al.
patent: 5041397 (1991-08-01), Kim et al.
patent: 5211804 (1993-05-01), Kobayashi
patent: 5264076 (1993-11-01), Cuthbert et al.
Wolf., S., Silicon Processing, vol. 2, 1990, Lattice Press, pp. 189-194, 127-128, 229-236.
Wolf., S., et al., Silicon Processing, vol. 1, 1986, Lattice Press, pp. 182-194.
"A 2.3um.sup.2 Memory Cell Structure for 16Mb NAND EEPROMs," Shirota et al., Toshiba Corp., 1990 IEEE, IEDM pp. 90-103--90-106.
Chittipeddi Sailesh
Cochran William T.
AT&T Corp.
Quach T. N.
Rehberg John T.
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