Boots – shoes – and leggings
Patent
1994-12-21
1996-07-16
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364489, 364490, G06F 1700
Patent
active
055375804
ABSTRACT:
A method for fabricating an integrated circuit includes the steps of: (a) describing the functionality of an integrated circuit in terms of a behavioral hardware description language, where the hardware description language describes behavior which can be extracted as a state machine; (b) extracting a register level state machine transition table of the state machine from the hardware description language; (c) generating a logic level state transition table representing the state machine from the register level state machine description; (d) creating a state machine structural netlist representing the state machine from the logic level state transition table; and (e) combining the state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist including the state machine to provide a basis for chip compilation, mask layout and integrated circuit fabrication. The method results in a synchronous state machine being extracted from an register-transfer (RT) level representation taken from a scheduled behavioral hardware description language description such as a Verilog or VHDL. Behavioral hardware description language constructs such as "if", "case", "for" statements and sub-program calls can describe the state machine. A logic level state transition table represents each extracted state machine, and each extracted state machine includes control logic produced by previous synthesis phases such as data-path and memory synthesis.
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Giomi Jean-Charles
Tarroux Gerard
Nguyen Tan
Teska Kevin J.
VLSI Technology Inc.
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