Integrated circuit fabrication critical dimension control using

Details Integrated circuit fabrication critical dimension control using Integrated circuit fabrication critical dimension control using

1998-12-04

2000-09-19

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

430 5, 216 48, 216 67, H01L 21302

Patent

active

061211559

ABSTRACT:
The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or variation. Trim time is set in a plateau region of the critical dimension loss process curve.

REFERENCES:
patent: 3997367 (1976-12-01), Yau
patent: 5804088 (1998-09-01), McKee
"Trimming of Negative Electron Resist for Multilevel Metallization"; Hieke et. al; 10-82'; Microcircuit Engineering 82', abstract only.

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