Integrated circuit fabrication

Details Integrated circuit fabrication Integrated circuit fabrication

2000-11-30

2003-03-25

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S170000, C438S189000, C438S234000, C438S235000, C438S236000, C438S423000, C438S440000, C438S506000, C257S555000, C257S557000, C257S565000

Reexamination Certificate

active

06537887

ABSTRACT:

FIELD OF THE INVENTION
This invention relates, in general, to semiconductor integrated circuit technology and, in an illustrative embodiment, to integrated circuits that include bipolar or BiCMOS devices.
BACKGROUND OF THE INVENTION
Many modern integrated circuits utilize both bipolar and MOSFET (e.g., CMOS, NMOS, or PMOS) devices on a single chip. Such integrated circuits (when they combine bipolar and CMOS) are often termed “BiCMOS”. Fabrication of BiCMOS (or even BiNMOS or BiPMOS) integrated circuits poses special problems for the process designer because certain process steps (e.g., heating, deposition, etching, etc.) that may facilitate formation of bipolar devices may adversely effect formation of MOS devices.
One common problem with integrated circuit fabrication is the unwanted growth of oxide, specifically around window devices. Suppressing or suspending oxide growth around the window area should improve the uniformity of the wafers containing these devices. However, current means of suppressing or suspending oxide growth involve using low temperature (450° C.) during the wafer push into the furnace followed by high temperature (615° C.) for emitter poly deposition. These techniques are flawed in that they decrease wafer throughput and shorten furnace lifetimes.
Those concerned with the development of integrated circuit technology have consistently sought improved methods of integrated circuit fabrication. In order to increase throughput and uniformity, it is desirable to discover new methods of suppressing or suspending oxide growth during circuit fabrication.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an integrated circuit with a nitrogen implanted emitter window.
The present invention also provides a method of making an integrated circuit with minimal oxide growth wherein nitrogen is implanted into the emitter window after the emitter window etch, but prior to emitter conductor deposition.


REFERENCES:
patent: 5789305 (1998-08-01), Peidous
patent: 6194288 (2001-02-01), Fahn
patent: 6372585 (2002-04-01), Yu
patent: 6372596 (2002-04-01), Havemann

Affiliated with

Also associated with

Rating

Integrated circuit fabrication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit fabrication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit fabrication will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3084498