Integrated circuit fabrication

Details Integrated circuit fabrication Integrated circuit fabrication

1993-10-29

1995-11-21

Quach, T. N.

Fishing, trapping, and vermin destroying

437 56, 437192, 437193, 437200, 437956, 148DIG20, H01L 21253, H01L 21335

Patent

active

054686695

ABSTRACT:
A semiconductor integrated circuit, and process for its manufacture, are disclosed which contains both n.sup.+ and p.sup.+ gates that do not pose a risk of dopant interdiffusion. Both n.sup.+ and p.sup.+ gates may be fabricated by conventional means. The gate structures are severed over the tub boundaries. A titanium nitride interconnective layer is deposited and patterned over the gates. The interconnective layer preserves connectivity between the n.sup.+ and p.sup.+ gates without risk of deleterious dopant interdiffusion.

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patent: 4463491 (1984-08-01), Goldman et al.
patent: 4555842 (1985-12-01), Levinstein et al.
patent: 4931411 (1990-06-01), Tigelaar et al.
patent: 4977102 (1990-12-01), Ema
Wolf, Silicon Processing, Lattice Press, 1990, vol. 2, pp. 587-593, 623-635.
Wolf, Silicon Processing, Lattice Press, 1986, vol. 1, pp. 384-386.

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