Integrated circuit embedded with single-poly non-volatile...

Details Integrated circuit embedded with single-poly non-volatile... Integrated circuit embedded with single-poly non-volatile...

2005-07-19

2005-07-19

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280

Reexamination Certificate

active

06920067

ABSTRACT:
A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+doped drain region and a first P+doped source region, the second PMOS transistor includes a single-poly select gate and a second P+doped source region, and the first P+doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

REFERENCES:
patent: 5732207 (1998-03-01), Allen et al.
patent: 5761121 (1998-06-01), Chang
patent: 5896315 (1999-04-01), Wong
patent: 6157574 (2000-12-01), Kalnitsky et al.

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