Integrated circuit electrostatic discharge input protection

Details Integrated circuit electrostatic discharge input protection Integrated circuit electrostatic discharge input protection

1987-06-15

1989-02-21

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 58, 361 91, 357 2313, H02H 904

Patent

active

048070807

ABSTRACT:
Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents generated by electrostatic discharge through handling or otherwise, is provided by a circuit structure at each input pad of an integrated circuit chip. One such feature includes the use of a barrier layer of polysilicon material to make an electrical contact between source and drain diffusions of a protective transistor and their respective aluminum conductors, in order to increase the amount of current that can be handled at such contacts without the aluminum conductor fusing though a diffusion into the substrate. Another such feature is to provide an initial, and perhaps only, protective transistor that has a very narrow channel between source and drain diffusions to allow a reversible breakdown to reduce the voltage across it to within, or nearly within, the maximum voltage that the protected thin gate oxide transistor can handle without being damaged. Further, current concentrations in the protective transistor are minimized by the use of elongated diffusions and associated solid elongated conductors having rounded corners.

REFERENCES:
patent: 4541002 (1985-09-01), Shimada
patent: 4605980 (1986-08-01), Hartranft et al.
Roundtree et al., "NMOS Protection Circuitry," IEEE Transactions on Electron Devices, vol. ED-32, No. 5, May 1985.

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