Integrated circuit electromigration monitor

Details Integrated circuit electromigration monitor Integrated circuit electromigration monitor

1992-04-03

1993-11-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437170, 437957, H01L 2166

Patent

active

052643778

ABSTRACT:
The electromigration characteristics of integrated circuit conductors are determined by passing a high current for a short period of time through an inventive test structure. This provides a rapid test in a more accurate manner than with the prior art SWEAT (Standard Wafer-level Electromigration Accelerated Test) structure. The test results have been found to be well correlated with long-term low current electromigration tests. A sensitive differential test may be implemented that determines the effects of topography features. The inventive test technique can be performed on every wafer lot, or even every wafer, so that adjustments to the wafer fabrication process can be rapidly implemented.

REFERENCES:
patent: Re32625 (1988-03-01), Schwarz et al.
Blake et al., "Test Site Technology in Integrated Circuits", IBM Tech. Disc. Bull., vol. 10, No. 2, Jul. 1967, p. 168.
American Society for Testing and Materials, "Standard Guide for Design of Flat, Straight-Line Test Structures for Detecting Metallization Open-Circuit or Resistance-Increase Failure Due to Electromigration", Designation F 1259-89 (Annual Book of ASTM Standards, vol. 10.04), 1989.
Proceedings of the IEEE International Reliability Physics Symposium (1985), pp. 100-107.
"Step Spacing Effects on Electromigration", by A. S. Oates; to be published in the Proceedings of the IEEE International Reliability Physics Symposium (1990).

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