Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-04-25
2004-03-30
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06714032
ABSTRACT:
STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
(Not Applicable)
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved method for testing integrated circuits (ICs) during the IC fabrication process. More specifically, the present invention relates to an improved method for using quiescent or transient current signatures to test for defective ICs during the IC fabrication process.
2. Description of the Related Art
Integrated circuits consist of a number of interoperable circuits fabricated on a silicon substrate. The number of interoperable circuits that can be supported by a substrate continues to grow as the art of IC manufacturing advances. Currently, it is not uncommon for an IC to include several million transistors configured into tens of thousands of interoperable circuits. While increasing the number of circuits that can be fabricated on a single IC allows designers to design smaller and faster products, such increases present the IC manufacturer with challenges in manufacturing fault-free ICs. One such challenge for manufacturing fault-free ICs is the difficulty in testing these ICs for defects in an accurate and efficient manner.
To facilitate IC testing, many different IC testing methodologies have been developed. These testing methods have been developed for evaluating any of a number of types of ICs, such as complimentary metal-oxide semiconductor (CMOS) ICs. These testing methods analyze the failure rate of the tested ICs so that substandard ICs are not distributed in the marketplace. These testing methodologies can be either built into the IC itself, or can be performed through the use of separate testing mechanisms.
Testing is usually performed to ensure proper logical operation of the ICs and to detect manufacturing defects in the components comprising the ICs. To ensure proper logical operation of the IC, the IC is stimulated using known test patterns and is monitored to determine its output response. If the resulting output response of the IC is as anticipated, it is assumed that the IC is functioning properly. For VLSI circuits, tens to hundreds of megabytes of test patterns are needed to test most of the IC. Such testing is extremely time consuming.
Testing methods include built-in-self test (BIST) circuitry, accelerated life testing (“burn-in”), functional testing, stuck-at fault (SAF) testing, quiescent current (I
ddq
) testing, and transient current (I
ddt
) testing, among other testing methods.
BIST circuitry is incorporated into the IC itself, and can constitute a significant portion of the circuitry on an IC, i.e., approximately 17%-30%. This BIST circuitry internally stimulates the IC in which it is incorporated, and measures the corresponding output response resulting from the stimulus. The problem with BIST circuitry is that it requires more hardware space on the IC as the number of gates or nodes on the IC increases. Thus, as the complexity of the IC increases, the amount of space on the IC surface necessary for testing circuitry increases. This can be extremely inefficient when the size of the IC is a concern.
Burn-in can be used to accelerate identification of latent IC defects created during either the IC fabrication process or the semiconductor assembly process. One example of a latent IC defect caused during the IC fabrication process is a defect in an oxide film of the IC, such as a pinhole in the gate oxide, while an example of a latent IC defect caused during the semiconductor assembly process is a crack in the sealing resin. Identifying and removing latent defects allows for higher reliability circuits to be supplied to IC users.
In the IC fabrication process, burn-in is performed by applying an environmental stress, such as high temperature/voltage to an IC being tested. During and/or after the application of this stress, the IC is monitored to determine whether it performs properly. The application of this environmental stress to the IC allows for the reliability of the assembled device (IC) to be ascertained.
The amount of time for which the electrical or environmental stress is applied to the IC must be determined experimentally. The stress should function to destroy or degrade performance in those ICs that are inherently defective, while having little or no effect at all on those ICs which are fault-free. Depending on the length of time for which the burn-in stress is applied to the IC, and the sample number of ICs that are burned-in, the burn-in process can result in anywhere from 5%-40% of the cost of producing an IC. In order to become more competitive in the marketplace, more efficient methods of failure analysis testing should be developed.
Another IC testing method is logic response stuck-at-fault (SAF) testing. Logic response SAF testing involves the application of stimuli to the inputs of a particular IC, and the examination of the IC outputs to determine if a particular internal fault exists in the IC. If a Stuck-at-fault exists for a given circuit node, that node will not toggle, and will be “stuck-at” either a 1 or a 0, such that the actual output response of the IC will not match the expected response. There are, however, some inherent problems with using logic response SAF testing to identify faults in a given IC. For example, it is difficult and costly to generate a sufficient number of input signal test vectors to detect a desired level of fault coverage Fault coverage is the percentage of all possible faults in a given IC that can be tested by a given set of test vectors. Also, it is extremely time consuming to measure the response of every circuit found in the IC. Furthermore, in circuits with inherently low controllability, such as those with random logic control circuits or those circuits with asynchronous designs, a large number of internal faults in the IC may not be stimulated, and will not be detectable at the output regardless of the particular stimuli applied. The desired fault coverage therefore may not be obtained for ICs using the SAF test. Secondly, many physical defects in an IC, such as bridging, gate oxide shorts, and spot defects, might not be detected using the SAF test. These defects can cause indeterminate logic levels at the defect site, and therefore cannot be detected by any logic testing method.
One alternative to the SAF test involves the use of a technique known as scan design. The scan design technique requires test structures to be incorporated into the IC in order to facilitate testing. Scan testing adds controllability to defective nodes, but does not guarantee that the defective response can be observed at the device outputs. Thus, as is the case with functional and SAF tests, stuck-at faults and physical defects such as bridging, gate oxide defects and spot defects, might not be detected by scan testing.
Another problem with adding scan structures into the IC is that these structures consume IC space and power—much like BIST. Additionally, depending on the placement of these scan structures, timing problems may be introduced into the IC. As a result, scan structures may be difficult to incorporate into an existing IC design. Thus, an IC typically must be designed from the outset to incorporate acceptable scan structures.
Another method of failure analysis testing is quiescent current, or I
ddq
, testing. Over the last 15-20 years, research has shown that a very effective method for screening out defective ICs, including certain CMOS-designed devices, that are at a filly static (or quiescent) state is to determine whether or not these ICs have higher than nominal background current levels. Fully static means that no internal nodes of the IC are changing state or switching, i.e., toggling between 0 and 1. Furthermore, nominal background current means that the fully static IC only draws current in its quiescent state due principally to sub-threshold and reverse-bias junction leakage of transistors, and the IC is in a low current state. Since a logical circuit can be represented by an in
Agere System Inc.
Cuneo Kamand
Kobert Russell M.
LandOfFree
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