Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-04-01
2001-01-23
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S170000, C327S108000, C327S437000, C326S087000, C326S027000
Reexamination Certificate
active
06177819
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits (ICs). More particularly, the invention relates to a driver circuit for an IC.
BACKGROUND OF THE INVENTION
In integrated circuits, signals are often transmitted on signal lines for relatively long distances across the IC. The resulting resistance and capacitive loading introduces delay to the signal. For some heavily loaded signal lines, the delay is crucial to the function of the circuit. Therefore, such lines are often buffered, i.e., driver circuits are provided that accept an input signal at an input terminal and mirror the input signal as an output signal on an output terminal, with increased drive capability. Available driver circuits, however, impose a delay between the input and output signals that must be taken into account when designing ICs. Therefore, while the overall path delay can be reduced by using a driver circuit, the path delay cannot be reduced beyond the delay through the driver circuit.
In field programmable gate arrays (FPGAS), general interconnect lines are provided that can be programmed to be used for many different functions. (One such FPGA, the Xilinx XC4000™ Series FPGA, is described in detail in pages 4-5 through 4-69 of the Xilinx 1998 Data Book entitled “The Programmable Logic Data Book 1998” (hereinafter referred to as “the Xilinx Data Book”), published in 1998 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) The signals on these general interconnect lines may have a high or low fanout, and may be of greater or lesser importance in determining the operating frequency of the design. Therefore, the need for buffering on such lines is difficult to predict. As a consequence, the longer general interconnect lines are usually buffered at all times in order to accommodate the worse case scenario. A signal traversing a large number of these buffers (i.e., a signal routed on a succession of programmably coupled general interconnect lines) incurs more delay than a signal traversing a smaller number of buffers. Therefore, the two signals are “skewed” relative to one another. This skew considerably complicates the task of implementing time-critical circuits in FPGAs.
Therefore, it is desirable to provide a buffer having a zero delay, so that a difference in the number of buffers traversed does not introduce skew between two signals. It is further desirable to provide an IC driver circuit having a negative delay, to compensate for delays in logic circuits on a signal path. It is yet further desirable to provide an IC driver circuit having an adjustable delay, so that delays in different paths can be adjusted to minimize skew.
It is also desirable to provide an IC driver circuit having a low noise sensitivity, and further to provide an IC driver circuit that it is programmably either high-speed (low delay) or noise-insensitive.
SUMMARY OF THE INVENTION
The invention provides an IC driver circuit having an adjustable trip point. A control circuit adjusts the trip point of the driver circuit during operation based on the state of the output signal, thereby providing higher speed and/or lower noise sensitivity.
A first embodiment of the driver circuit comprises an input terminal, an output terminal, a control circuit, two switch circuits, two pullup circuits, two pulldown circuits, and a delay element. The output terminal is coupled to each pullup and pulldown circuit. The input terminal is coupled to the first pullup circuit and through the first switch circuit to the second pullup circuit. The input terminal is also coupled to the first pulldown circuit and through the second switch circuit to the second pulldown circuit. The control circuit controls the switch circuits to either couple or decouple the input terminal from the second pullup and pulldown circuits, depending on the previous state of an output signal on the output terminal. The previous state of the output signal is determined by coupling the output signal to the control circuit through the delay element. In some embodiments the delay element is omitted, because the control circuit itself supplies sufficient delay on the output signal.
The driver circuit automatically adjusts the trip point of the circuit based on the state of the output signal (and thus, by inference, on the state of the input signal), by coupling and decoupling the second pullup and pulldown circuits from the input terminal using the first and second switches. This coupling/decoupling also ensures that the output signal has a shorter rise/fall time than the input signal. In one embodiment, the output signal reaches a midpoint voltage level (i.e., VCC/2) at the same time that the input signal reaches the same level, thereby providing a zero delay through the driver circuit. In another embodiment, the output signal reaches the midpoint voltage level before the input signal does so. In this embodiment, the driver circuit has, in effect, a negative propagation delay.
In a second embodiment, the first and second switches are controlled to ensure low noise sensitivity, rather than high speed. Therefore, the driver circuit acts as a Schmitt trigger.
In a third embodiment, the control circuit further comprises one or more control input terminals. Control signals received on these terminals determine which of two or more operating modes is followed by the control circuit. These modes may include, for example, a high-speed mode (as in the first embodiment) and a noise-insensitive mode (as in the second embodiment).
In other embodiments of the invention, the first switch circuit is disposed between the output terminal and the second pullup, while the second switch circuit is disposed between the output terminal and the second pulldown.
REFERENCES:
patent: 4612466 (1986-09-01), Stewart
patent: 5894238 (1999-04-01), Chien
“The Programmable Logic Data Book”, copyright 1998, available from Xilinx, Inc. at 2100 Logic Drive, San Jose, California 95124, pp. 4-5 to 4-69.
Cartier Lois D.
Le Dinh T.
Xilinx , Inc.
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