Excavating
Patent
1990-01-25
1992-06-30
Beausoliel, Robert W.
Excavating
371 221, G06F 1100
Patent
active
051270080
ABSTRACT:
A method and apparatus for designing very large scale integrated circuit devices, most particularly level sensitive scan design (LSSD) devices, by inclusion of a plurality of distributed delay lines originating at input terminals of the device, and controlling the inhibiting and enabling of driver circuits connected to the output terminals of the device, as required to regulate operation of device drivers during a plurality of testing operations.
REFERENCES:
patent: 4782283 (1988-11-01), Zasio
patent: 4862068 (1989-08-01), Kawashima
patent: 4879718 (1989-11-01), Sanner
patent: 4931723 (1990-06-01), Jeffrey
Bassett Robert W.
Gillis Pamela S.
Panner Jeannie T. H.
Stout Douglas W.
Turner Mark E.
Beausoliel Robert W.
International Business Machines - Corporation
Moore J. Dennis
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