Integrated circuit die I/O cells

Details Integrated circuit die I/O cells Integrated circuit die I/O cells

2003-04-09

2004-04-06

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S779000, C257S784000

Reexamination Certificate

active

06717270

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to integrated circuit (IC) die and specifically to I/O circuitry for IC die.
2. Description of the Related Art
An IC die may include bond pads located on its surface for coupling the circuitry of the IC die to external structures. In one example of a packaged IC, bond pads of an IC die are coupled to bond fingers of a package substrate via bond wires. The bond fingers are coupled to balls located on the packaged IC surface, such as with a ball grid array (BGA) packaged IC.
As integrated circuit technology advances, there is a desire to increase the amount of circuitry in a die, increase the operating speed of the die circuitry, and decrease the size of the die. An increase in the amount of circuitry along with an increase in operating speed may create a push for more bond pads on a die, wherein the decrease in size of the die reduces the amount of space available for these bond pads.
Furthermore, as the amount of circuitry increases and the die size decreases, the process to design an IC die becomes more complicated. In order to increase the efficiency of the IC die design, the circuitry of an IC die may be designed with multiple standardized design blocks of circuitry. For example, an I/O cell of an IC die may be designed from an I/O cell standardized design block.
What is needed is an efficient die design that enables the utilization of standardized design blocks for I/O cell design while increasing the efficiency of the bond pad layout.


REFERENCES:
patent: 5514892 (1996-05-01), Countryman et al.
patent: 6008542 (1999-12-01), Takamori
patent: 6037669 (2000-03-01), Shu et al.
patent: 6121690 (2000-09-01), Yamada et al.
patent: 6174803 (2001-01-01), Harvey
patent: 6242814 (2001-06-01), Bassett
patent: 6291898 (2001-09-01), Yeh et al.
patent: 6329278 (2001-12-01), Low et al.
patent: 6476506 (2002-11-01), O'Connor et al.
patent: 6489228 (2002-12-01), Vigna et al.
patent: 2003/0218255 (2003-11-01), Park et al.
patent: 2584259 (1987-01-01), None
Yong et al., U.S. patent application S/N 10/097,036 entitled “Semiconductor Device Having a Bond Pad and Method Therefor,” filed Mar. 13, 2002, Group Art Unit 2811 and assigned to assignee hereof.
Downey et al., U.S. patent application S/N 10/304,416 entitled “Semiconductor Device Having a Bond Pad and Method Therefor,” filed Nov. 26, 2002, Group Art Unit 2811 and assigned to assignee hereof.
Downey et al., U.S. patent application S/N 10/097,059 entitled “Semiconductor Device Having a Wire Bond Pad and Method Therefor,” filed Mar. 13, 2002, Group Art Unit 2818 and assigned to assignee hereof.

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