Integrated circuit die having an interference shield

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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Details

C257S659000, C257S700000, C257S758000, C257SE23128, C257SE23114

Reexamination Certificate

active

07151011

ABSTRACT:
A package for housing a device (e.g., an integrated circuit chip or die) includes a Faraday cage. The Faraday cage is at least partially formed in the integrated circuit die. The die includes conductive vias and solder balls surrounding a circuit. The package can be a ball grid array (BGA) package or flip chip package. The package substrate can include a ground plane.

REFERENCES:
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patent: 5592391 (1997-01-01), Muyshondt et al.
patent: 5955789 (1999-09-01), Vendramin
patent: 5986340 (1999-11-01), Mostafazadeh et al.
patent: 6130483 (2000-10-01), Shizuki et al.
patent: 6166403 (2000-12-01), Castagnetti et al.
patent: 6229404 (2001-05-01), Hatanaka
patent: WO 97 35344 (1997-09-01), None

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