Active solid-state devices (e.g. – transistors – solid-state diode – With shielding
Reexamination Certificate
2001-02-16
2002-11-26
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With shielding
C257S700000, C257S758000
Reexamination Certificate
active
06486534
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates generally to integrated circuits (ICs) and packages for integrated circuits. More specifically, the present specification relates to integrated circuits having improved electromagnetic shielding properties.
BACKGROUND OF THE INVENTION
Integrated circuit packages generally contain integrated circuit chips or die-containing densely packed circuits. Large numbers of electronic circuits placed in close proximity on an integrated circuit die can cause electromagnetic interference. It is desirous to prevent circuits within an integrated circuit from dispersing energy into adjacent cells or circuits.
One system or circuit can radiate energy into another system or circuit and disrupt the functionality or operation of the other circuit. Radiation or other energy can be disbursed by substrate coupling, through common ground, or through common power supplies. The energy can induce spurious signals in neighboring circuits or even prevent the operation of other circuit components.
The interference problem is a particular problem at high frequencies (HF) and radio frequencies (RF). Electromagnetic interference between circuits on an integrated circuit can also be a problem at lower frequencies.
Heretofore, electromagnetic interference between circuitry has been prevented by limiting the number of systems or circuits on a chip. Each chip is generally associated with a single circuit that is a source or is sensitive to electromagnetic radiation. Each chip is packaged and that package can be externally shielded, such as, in a Faraday cage.
Limiting the number of circuits on the chip increases costs of the entire system because the system must employ more chips. In addition, the use of individual Faraday cages for each package increases the cost of the system. Shielding the chip also increases manufacturing and assembly costs. Further, the entire size of the system is increased by the increased number of packaged chips and the external Faraday shielding.
An example of conventional electromagnetic shielding techniques is disclosed in U.S. Pat. No. 5,986,340 which describes a ball grid array (BGA) package. The package includes an external Faraday cage formed around the integrated circuit die. The external Faraday cage is comprised of a heat sink surrounding the integrated circuit die and a metal plate on an upper peripheral surface of the heat sink.
U.S. Pat. No. 5,986,340 is similar to U.S. Pat. No. 5,955,789 and discloses a plastic ball grid array (BGA) electronic package in a cavity down configuration. The package includes an active element mounted on a package substrate and is for use in HF applications. An external Faraday cage is realized to protect the active element from external HF interferences. A row of solder balls connected in a zig-zag fashion on a bottom of the package substrate and platedthrough holes through the package substrate form lateral sides of the external Faraday cage. The top side of the external Faraday cage is formed of a metal cap and the bottom side of the external Faraday cage is formed by a ground plane of the main board. The package in U.S. Pat. No. 5,955,789 does not provide shielding within the integrated circuit (IC) die.
Accordingly, there is a need for a package system that includes an integrated Faraday cage. Further, there is a need for a Faraday cage which utilizes internal chip structures. Further still, there is a need for a die for use with a flip chip package that includes a low-cost electromagnetic shield. Yet further, there is a need for a chip with electromagnetic interference protection that is conducive to advanced packaging systems, such as, BGA and flip chip packages.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to an integrated circuit package. The integrated circuit package includes an integrated circuit and a package substrate. The integrated circuit includes a first circuit and at least one second circuit. The first circuit is surrounded on lateral sides by a plurality of conductive vias. The package substrate has a ground plane. The conductive vias and the ground plane protect the second circuit from electromagnetic interference.
Another exemplary embodiment relates to an integrated circuit for mounting onto a flip chip package. The integrated circuit includes a semiconductor substrate, a plurality of metal layers, and a plurality of conductive vias. A first circuit is within a perimeter defined by the conductive vias and a second circuit is disposed outside the perimeter. The conductive vias provide electromagnetic shielding.
Still another embodiment relates to a method of providing a Faraday cage for an integrated circuit die contained in a package. The method includes providing conductive vias about a periphery of a circuit in the integrated circuit die, and mounting the integrated circuit die on a package substrate. The conductive vias are electrically coupled to a conductive plane of the package substrate.
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patent: 6229404 (2001-05-01), Hatanaka
patent: 10112517 (1998-04-01), None
Sridharan Guruswami M.
Sridharan Kartik M.
Ashvattha Semiconductor Inc.
Foley & Lardner
Wilson Allan R.
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