Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2002-05-17
2003-09-30
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S786000, C257S750000, C438S401000
Reexamination Certificate
active
06628001
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to an integrated circuit die having alignment marks in the bond pad regions and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
It is well known that integrated circuit fabrication on semiconductor wafers requires the formation of precise electrical interconnections to create operative components in very large scale integration (VLSI) and ultra large scale integration (ULSI) circuits. Equally well known is that the patterns defining such interconnections are typically created by optical lithographic processes that require precise alignment with each circuit level of a semiconductor wafer to accurately interconnect the devices located in those levels.
Conventionally, alignment of the pattern on one layer to those of previous layers is done with the assistance of special alignment patterns, provided through alignment marks, designed onto each mask level. When these alignment marks are precisely aligned, the remainder of the circuit patterns are also correctly aligned. The adjustment of the image of the mask being exposed to the previously produced patterns was originally performed by human operators, who compared the image locations under a microscope and adjusted the position of the mask to bring it into alignment with the wafer patterns. Decreasing feature sizes and the increasing number of alignments per wafer, however, have promoted the development of automatic alignment systems for use with projection photolithographic machines commonly called “steppers”.
Typical automatic alignment procedures involve the use of alignment marks formed in the same level of the semiconductor wafer where the active regions of each die are formed. In addition, such alignment marks are typically in the “kerfs” or “streets” that separate the individual dies formed on the semiconductor wafer. The streets form a grid-like pattern across a semiconductor wafer, dividing each of the dies formed therein. When manufacturing is completed, the dies are separated by cutting or sawing them apart, with the streets providing the guides for the blades.
In conventional alignment mark designs, the overall dimensions of the marks are generally large when compared to the dimensions of other areas on the wafer. Since the alignments marks are typically located in the streets, the larger the alignment marks are made, the larger the streets between the dies become. Those skilled in the art understand that as street size increases, the die yield of the semiconductor wafer decreases because of the increase in wafer surface area occupied by the streets. In view of the costs associated with wafer manufacturing, wafer manufacturers are eager to substantially reduce the size of the alignment marks in order to increase the number of dies obtained from each wafer.
Unfortunately, if the alignment marks are made too small in an effort to reduce street size, existing steppers have trouble detecting the marks, in some cases missing them altogether. More specifically, steppers are typically manufactured with the ability to detect a minimum alignment mark size. As a result, the overall size of the alignment marks may not be easily decreased by the wafer manufacturer, beyond this minimum size, without impacting the alignment mark detection of conventional the steppers. In addition, stepper manufacturers are typically unwilling to endure the expense of redesigning steppers capable of detecting alignment marks significantly smaller than those typically found on today's semiconductor wafers.
Accordingly, what is needed in the art is an integrated circuit die having alignment marks detectable by conventional steppers, and a method of manufacturing such alignment marks, that does not suffer from the deficiencies of the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die includes a bond pad region located between the circuit perimeter and an outer perimeter of the die. An alignment mark is located within the bond pad region.
In another aspect, the present invention provides a method of manufacturing a die located on a semiconductor wafer, which includes forming a circuit region located within a circuit perimeter of the die. The method further includes forming a bond pad region located between the circuit perimeter and an outer perimeter of the die, and creating an alignment mark located within the bond pad region.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention.
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Chittipeddi Sailesh
Vasudevan Keelathur N.
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