Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2005-06-22
2009-06-02
Cao, Phat X (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S780000
Reexamination Certificate
active
07541674
ABSTRACT:
An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent pad or pads is at least the minimum required for wire bond assembly. For wire bond assembly a passivation layer exposing all pads is provided, whereas for flip-chip assembly a passivation layer exposes only certain pads so that conductive bumps may be provided. The provision of pads complying with the minimum spacing requirements for both flip-chip and wire bond assembly enables a “dual purpose” (e.g. one set of pads being for normal production and another set for testing purposes) die to be produced without any increase in die size.
REFERENCES:
patent: 5155065 (1992-10-01), Schweiss
patent: 5228951 (1993-07-01), Pradel
patent: 5381307 (1995-01-01), Hertz et al.
patent: 5641946 (1997-06-01), Shim
patent: 5734199 (1998-03-01), Kawakita et al.
patent: 5757082 (1998-05-01), Shibata
patent: 5801450 (1998-09-01), Barrow
patent: 6107685 (2000-08-01), Nishiyama
patent: 6175157 (2001-01-01), Morifuji
patent: 6265783 (2001-07-01), Juso et al.
patent: 6320254 (2001-11-01), Liou et al.
patent: 6444563 (2002-09-01), Potter et al.
patent: 6972494 (2005-12-01), Addinall et al.
patent: 0 481 889 (1991-10-01), None
patent: 0 588 481 (1993-08-01), None
Parent case U.S. Appl. No. 09/639,288, filed Aug. 15, 2000, entitled “Improvements in or Relating to Integrated Circuit Dies”; to Ross Addinall, et al., allowed on Apr. 7, 2005.
Addinall Ross
Davies Gareth Rhys
Agere Systems Inc.
Cao Phat X
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