Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-06-29
2003-12-16
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000, C257S786000, C257S773000, C257S737000, C257S738000, C257S780000, C257S778000, C257S698000
Reexamination Certificate
active
06664620
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits and packages. More particularly, the present invention relates to an integrated circuit and/or a grid array package having a progressively variable pitch.
2. Description of Related Art
Over the years, the electronics industry has minimized the size of integrated circuit chip designs. As integrated circuits become more dense and therefore smaller, the packaging of integrated circuit becomes more complex. As a consequence, more and more input and output (I/O) connections become available for use with a single integrated circuit. For example, an integrated circuit with a size of 0.5 inches square can easily require 400 or more connections.
Some of the latest microprocessor devices are packaged in land grid array (LGA) packages or modules. The LGA package style comprises an array of planar, typically rectangular or circular, conductive pads located on an underside of the IC package for surface contact with leads on a PCB. The array of pads is typically in a multiple row, multiple column arrangements, creating a matrix of surface contacts. LGA packages are ideal for devices such as microprocessors. The LGA package uses pads instead of pins, which are more susceptible to damage, to provide the required electrical connections between the integrated circuit device and the circuit board, allowing the pitch of the electrical contacts to be very small.
A package for carrying an integrated circuit die having a high density of input/output pads will typically include signal traces that fan out with distance from the die. The bond wires have inner lead ends connected to the input/output pads of the die and have outer lead ends that connect to the inner trace ends of the signal traces which typically serve as bond sites. By fanning out with departure from the die, the array of signal traces may be considered to be a “space transformer.” The ends of the signal traces furthest from the die may be spaced apart by greater distances, allowing the use of vias and solder bumps. The space transformation accommodates the high-density input/output pads of the integrated circuit die.
However, various constraints limit the number of signal traces that can be fabricated on an integrated circuit die or package using an array layout. Industry standards and other process issues impose specific requirements as to the spacing between electrical contacts (e.g., electrically conductive bumps such as solder bumps), thereby restricting the spacing between the vias that electrically connect the signal traces to the solder bumps. The spacing restriction limits the number of signal traces that can fit between the vias which, in turn, limits the number of signal traces that can be used to carry signals to and from the die. Current fabrication technology imposes minimum pitch requirements for signal traces to attain satisfactory yields and to ensure mechanical and electrical reliability. The limitation on the maximum number of usable signal traces limits the maximum number of solder bumps, thereby placing a ceiling on the number of signals that a particular die and/or package can provide.
It is necessary in the attempts to increase the number of signals a particular package can provide to increase the number of signal traces used to carry signals to and from the die. Currently, present design rules provide for designing packages having an approximate 50 mil fixed pitch for every row and integrated circuit dies having an approximate 10 mil fixed pitch for every row. This results in approximately 236 signal traces for a given routing layer. One method of increasing the number of signal traces per given routing layer is through use of a variable pitch design at every row of contacts.
SUMMARY OF THE INVENTION
The present invention discloses an integrated circuit die and/or package. In both cases, the package and/or die have a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.
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Bhattacharyya Bidyut K.
Siu William M.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Loke Steven
Parekh Nitin
LandOfFree
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