Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...
Reexamination Certificate
2000-01-11
2002-10-22
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With contact or metallization configuration to reduce...
C257S356000, C257S758000, C257S773000, C257S920000
Reexamination Certificate
active
06469360
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of microelectronics and more particularly to integrated circuit devices.
BACKGROUND OF THE INVENTION
As integrated circuit devices become more highly integrated, the distances between circuits formed on a semiconductor wafer are reduced. Accordingly, patterned layers formed on the semiconductor substrate have reduced spaces therebetween. When implanting such patterned layers, charge may accumulate on the structures of the patterned layer. This “charge-up” phenomenon may result in electric fields which damage the structures of these finely patterned layers. Anisotropic etching processes may also result in damaging charge accumulation. In particular, the thin insulating films used in polysilicon thin film transistor LCD processes can be readily damaged as a result of the “charge-up” phenomenon.
When ions are implanted into a wafer, the implanted ions collide with atoms of the wafer generating secondary electrons which are emitted from the wafer. The number of secondary electrons emitted varies according to the composition and the physical configuration of the wafer. In general, a larger number of secondary electrons are emitted from a conductor than from an insulator, and the number of secondary electrons emitted increases as the area of the structure increases. Referring to
FIG. 1
, for example, the number of secondary electrons emitted from the patterned polysilicon layers A and B is approximately two to four times greater than the number of secondary electrons emitted from the patterned oxide layer C.
While each of the patterned polysilicon layers A and B and the patterned oxide layer C are positively charged, the charge of polysilicon layer B is greater than that of polysilicon layer A because of the difference in the surface areas of the layers. Accordingly, a potential difference is generated between polysilicon layers A and B. The electric field resulting from this potential difference may be relatively strong when the two charged polysilicon layers are closely spaced.
The oxide layers C and the active region D between the charged polysilicon layers A and B may thus be affected by the electric field. If the electric field is strong enough, electrons from the oxide pattern C and the active region D may migrate to the polysilicon layers A and B. Furthermore, electrons from the active region D may be more easily subjected to migration than electrons from a nonconductive substrate E such as a quartz substrate. This migration of electrons may result in a deterioration of the oxide layer C and may even lead to the formation of a short circuit between the polysilicon layers A and B and the active region D.
In order to reduce damage resulting from this “charge-up” phenomenon, there have been proposed methods for showering the semiconductor structure with electrons after performing the ion implantation. Although this process can neutralize the charge of the structure, thus reducing the effects of charge-up, damage may still occur.
The layout of a semiconductor device which has been damaged as a result of the “charge-up” phenomenon is illustrated in
FIG. 2. A
long conductive pattern
14
and a short conductive pattern
10
are arranged adjacent to an active region
12
. When ions are implanted into a substrate having such a structure, secondary electron emission may occur, and the long and short conductive patterns
14
and
10
may become positively charged. Because the charge on the longer conductive pattern
14
(with a larger surface area) is greater than that of the shorter conductive pattern
10
(with a smaller surface area), a potential difference is generated between the conductive patterns
10
and
14
. The electric field resulting from this potential difference is strongest where the conductive patterns are most closely spaced.
An insulating film may be located between the active region
12
and the conductive patterns
10
and
14
. Portions of the active region
12
and the insulating film are thus located within the strongest portions of the electric field between the conductive patterns
10
and
14
. The insulating film may be relatively thin, and more particularly, may be thinner than the space between the conductive patterns
10
and
14
. Electrons from the insulating film and the active region
12
may thus migrate to the conductive patterns
10
and
14
under the influence of the electric field.
The electric field may be directed from the longer pattern
14
toward the shorter pattern
10
with the electrons migrating toward the longer conductive pattern
14
. If the distance between the conductive patterns
10
and
14
is relatively short, an electric field with sufficient strength to damage the insulating film may be generated. Accordingly, the conductive patterns
10
and
14
may be connected to the active region
12
through damaged portions of the insulating film. Because the active region
12
is conductive, the conductive patterns
10
and
14
are thus shorted. Even if not shorted, the migration of electrons from the active area to the conductive patterns may result in a decreased conductivity of the active region.
As discussed above, the insulating film of a conventional semiconductor device may be damaged due to the “charge-up phenomenon”. The resulting short circuits may reduce the yield of the semiconductor devices thus produced.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit methods and structures.
It is another object of the present invention to provide methods and structures for reducing damage due to the “charge-up” phenomenon.
It is still another object of the present invention to provide methods and structures for increasing yields of semiconductor devices.
These and other objects of the present invention are provided by a method for fabricating an integrated circuit device including the steps of forming first and second conductive regions on a substrate. The second conductive region is divided into first and second subregions, and the first subregion is adjacent the first conductive region. Furthermore, the surface area of the first subregion is not more than ten times greater than the surface area of the first conductive region. The first and second subregions are then electrically connected to complete the second conductive region. Accordingly, the substrate can be processed with adjacent conductive regions having approximately equal size, with conductive subregions being connected at a later time.
More particularly, the step of electrically connecting the subregions can be preceded by the step of bombarding an ion stream on the first and second conductive regions. The charge accumulated on the first subregion and the charge accumulated on the first conductive region are not so different that a damaging electric field is generated therebetween. More particularly, the bombarding step can include implanting a stream of ions. Damage due to the “charge-up” phenomenon during ion implantation can thus be reduced.
The first and second conductive regions may be patterned layers of polysilicon. More particularly, these conductive regions may define gate electrodes of one or more field effect transistors. The steps of forming the first and second conductive regions may be preceded by the steps of forming an active portion of the substrate and forming an insulating layer on the active portion of the substrate. In particular, the first conductive region and the first subregion of the second conductive region can be formed on the insulating layer opposite the active portion of the substrate. In addition, the first and second subregions may define a conductive line and the electrically connecting step may include forming a metal connection between the first and second subregions.
A method of the present invention thus allows relatively long conductive lines to be formed adjacent relatively short conductive lines and implanted without causing significant damage as a result of the charge-up phenomenon. In particular,
Eckert II George C.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd
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