Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1994-10-14
1997-10-14
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257392, H01L 2978
Patent
active
056775504
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to semiconductor devices and, in particular, to the fabrication of thin film transistors and integrated circuits incorporating such transistors.
BACKGROUND OF RELATED ART
In designing circuits for integrated electronics it is an advantage to have more than one type of active device available--for example CMOS has n and p channel devices and most n-MOS integrated circuit fabrication processes allow selective variation of the threshold voltage, in particular with the simultaneous fabrication of enhancement and depletion mode devices. For an n-channel enhancement mode device the minimum current (off state) flows with zero applied gate voltage and is increased by applying a positive gate voltage (on state). Conversely, for a depletion mode device a negative gate voltage is applied to turn the device off whilst at zero gate voltage the device is in the on state.
In n-MOS circuits use of enhancement-depletion mode circuitry gives improved performance when compared with enhancement mode-only circuits, in terms of switching speed, output voltage levels, and power consumption.
As indicated above, improved circuit performance is possible if depletion mode devices are also available. Possible ways to produce depletion type thin film active devices are to increase the semiconductor film thickness for the depletion mode devices as compared to the enhancement mode devices, or to selectively add n-type dopant material into the channel region of the depletion mode devices. In either case additional process steps would be needed, involving the use of extra mask layers, and hence increased cost and reduced yield. Depletion and enhancement mode devices may also be produced by using different geometries of the CdSe layers without an additional mask step.
SUMMARY OF THE INVENTION
We have devised a process using cadmium selenide which produces a double gated n-channel enhancement mode device, combining the desirable characteristics of high speed operation due to the high carrier mobility, high on current and low off current.
It has been found possible to produce depletion-mode TFTs without any additional processing steps by biasing one of the gates of the device to control the threshold voltage of the device so that it has a suitable (negative) value and so that it operates as either a depletion mode device or as an enhancement mode device. Thus the TFTs can be made to be enhancement or depletion types as required, with both types co-existing in the same circuit.
No alterations to the fabrication process are needed, and no additional mask layers, merely a small variation in mask design to allow separate control of the potential of both gates of each of the TFTs. An externally applied voltage is applied to one gate of the depletion mode devices in the circuit to set the required threshold voltage.
According to the present invention there is provided an integrated circuit arrangement comprising a pair of insulated-gate transistor devices connectible in series wherein the first transistor of the pair is operable as a depletion-mode device whilst the second transistor of the pair serves as an enhancement-mode device.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be particularly described with reference to the accompanying drawings, in which:
FIG. 1 is a cross-section through a thin film transistor in accordance with a specific embodiment of the invention;
FIG. 2 shows electrical characteristics of the transistor of FIG. 1;
FIGS. 3A and 3B are circuit diagrams of an inverter; and
FIG. 4 shows electrical characteristics of this inverter.
DESCRIPTION OF PREFERRED EMBODIMENTS
Referring now to the drawings, FIG. 1 shows a cross-section through a thin film transistor in accordance with a specific embodiment of the present invention. A diffusion barrier 1 is formed on a substrate 3. The device has a bottom gate 5 separated by an insulator layer 7 from a layer of cadmium selenide 9. An n-channel region 11 is formed in this semiconductor layer. A pad contact 13 and column
REFERENCES:
patent: 4040073 (1977-08-01), Luo
patent: 4803530 (1989-02-01), Taguchi et al.
patent: 4963860 (1990-10-01), Stewart
patent: 5053347 (1991-10-01), Wu
Patent Abstract of Japan, vol. 007, No. 021 (E-155) 27 Jan. 1983 & JP, A, 57 180 177 (Tokyo Shibaura Denki KK) 6 Nov. 1982 see abstract.
IBM Technical Disclosure Bulletin, vol. 20, No. 12 May 1978, New York US p. 5352 F.F. Fang"TFT Structure with Electronically Adjustable Threshold".
Patent Abstract of Japan vol. 015, No. 229 (E-1076) 11 Jun. 1991 & JP, A, 30 66 159 (Mitsubishi Electric Corp.) 20 Mar. 1991--see Abstract.
IEEE Electron Device Letters, vol. 13, No. 1, Jan. 1992, New York US, pp. 17-19 Biing-Seng Wu et al "A Novel Depletion-Gate Amorphous Silicon thin-Film Transistor" see whole document.
British Technology Group Limited
Hardy David B.
Thomas Tom
LandOfFree
Integrated circuit devices including insulated-gate transistor d does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit devices including insulated-gate transistor d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit devices including insulated-gate transistor d will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1557237