Integrated circuit device with stand-by cancellation

Details Integrated circuit device with stand-by cancellation Integrated circuit device with stand-by cancellation

1991-01-23

1994-04-26

Bowler, Alyssa H.

Boots, shoes, and leggings

395550, 364143, 364270, 3642706, 3642719, 364DIG1, 364DIG2, 365229, G06F 302

Patent

active

053075005

ABSTRACT:
An integrated circuit device having a processing unit (3) with a plurality of input terminals (I1-In) and adapted to cancel its stand-by mode when a pulse-like control signal (A) having a predetermined duration is received by one of the input terminals. The integrated circuit device includes a plurality of external terminals (T1-Tn) for receiving signals and a plurality of control signal generating circuits (C1-Cn) each having an input connected to a corresponding one of the external terminals. Each control signal generating circuit (C1-Cn) has an output terminal connected to a corresponding one of the input terminals of the processing unit (3). Each of the control signal generating circuits has a D flip-flop (4) for, on receiving a pulse signal (R) for canceling the stand-by mode from the processing unit (3), elongating a duration of the pulse signal to a predetermined duration.

REFERENCES:
patent: 3843838 (1974-10-01), Wanek
patent: 4050096 (1977-09-01), Bennett et al.
patent: 4486827 (1984-12-01), Shima et al.
patent: 4538902 (1985-09-01), Inuzuka et al.
patent: 4802120 (1989-01-01), McCoy
patent: 4965793 (1990-10-01), Plozin et al.
patent: 5019966 (1991-05-01), Saito et al.
patent: 5043881 (1991-08-01), Hamazaki
patent: 5225989 (1993-07-01), Kawamura et al.
National Semiconductor, "Logic databook--vol. II," 1984, pp. 4-250 to 4-251.

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