Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-08-19
2001-05-29
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S141000
Reexamination Certificate
active
06239631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer, which fetches and latches an input signal in synchronization with a clock, and more particularly to an integrated circuit device having an input buffer capable of operating in correspondence with a highspeed clock.
2. Description of the Related Art
To achieve highspeed operation, an integrated circuit device like a highspeed synchronous DRAM has input buffers, which, in synchronization with a clock from the control side, receive and latch inputted signals, such as data, address, and control signals, supplied in synchronization with this clock. Such input buffers receive and internally latch the supplied input signals in synchronization with the rising edge of a clock supplied as a strobe signal. Therefore, the controller side can provide an input signal in synchronization with a clock, enabling the realization of highspeed operation without need for concern over problems such as propagation delay time within the circuit substrate on which the integrated circuit device is mounted.
FIG. 12
is a block diagram of input buffer elements of a conventional integrated circuit device. An integrated circuit device
1
has a clock buffer
10
, which receives a clock CLK, a clock compensating element
12
, which compensates the phase of an internal clock iclk outputted from the clock buffer
10
, and input buffers
20
,
21
,
22
, which, in synchronization with an internal clock clk outputted by the clock compensating element, receive an externally-supplied address Add, control signal &phgr;
CON
, and data signal DQ.
FIG. 13
is a timing chart showing the operation of the input buffer of FIG.
12
. As shown in
FIG. 13
, the input buffers
20
,
21
,
22
receive and internally latch supplied input signals Add, &phgr;
CON
, DQ in synchronization with the rising edge of an internal clock clk phase synchronized to an external clock CLK.
However, if, for example, the frequency of the synchronization clock CLK is around 200 MHz, an input buffer can reliably receive an input signal in synchronization with the rising edge of that clock CLK, but if, for example, the frequency of the synchronization clock CLK is a high frequency of 400 MHz, the operating speed of a input buffer reaches its limit, making a normal input signal capture operation impossible. Moreover, with a highspeed synchronization clock, there are cases in which the clock waveform is disturbed by such factors as noise, making the pulse width extremely narrow, with the result that an input buffer cannot reliably receive an input signal.
Accordingly, an object of the present invention is to provide an integrated circuit device having an input buffer capable of reliably capturing a supplied input signal in synchronization with a highspeed clock.
Furthermore, another object of the present invention is to provide an integrated circuit device having an input buffer capable of reliably receiving a supplied input signal in synchronization with a clock of a wide range from low speed to high speed.
SUMMARY OF THE INVENTION
To achieve the above-mentioned objects, one aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable capture of input signals.
Further, according to another aspect of the present invention, when a supplied external clock is a high frequency, input buffers operate in synchronization with frequency-divided internal clocks, and when an external clock is a low frequency, input buffers operate in synchronization with the external clock, thus enabling the input buffers to correspond with an external clock of a wide frequency range.
To achieve the above-mentioned objects, another aspect of the present invention is an integrated circuit device having input buffer, which receives and latches input signal in synchronization with a supplied clock, the integrated circuit device comprising: a frequency-dividing circuit for generating a plurality of different phase internal clocks by frequency-dividing the supplied clock; a plurality of input buffers for receiving and latching the input signal in synchronization with each of the plurality of internal clocks; and a combining circuit for combining the outputs of the plurality of input buffers.
One embodiment of the above-described invention is further characterized in that the combining circuit has a plurality of tri-state buffers, which constitute either a low impedance state including either an H level or an L level or a high impedance state in response to each of the outputs of the plurality of input buffers, and a common output latch circuit to which the outputs of the plurality of tri-state circuit buffers are supplied.
Another embodiment of the above-described invention is further characterized in that it also has a mode register in which a frequency-division control signal is set in accordance with the frequency of the supplied clock, and the frequency-dividing circuit, in accordance with the frequency-division control signal, performs a frequency division operation when the frequency of the supplied clock is higher than a predetermined frequency, and does not perform a frequency division operation when the frequency of the supplied clock is lower than the predetermined frequency. According to this invention, input signals can be reliably received in correspondence to a supplied clock of a wide frequency range.
Another embodiment of the above-described invention is further characterized in that it further has an internal clock inputting circuit, which changes a leading internal clock to the other level when the one level of the frequency-divided internal clocks overlaps, and the plurality of input buffers input the respective internal clocks via the internal clock inputting circuit. Because the invention is constituted so that the one level of the plurality of internal clocks does not overlap, the outputs from the respective input buffers can be prevented from contending with one another in the combining circuit.
REFERENCES:
patent: 4328588 (1982-05-01), Smithson
patent: 4692932 (1987-09-01), Denhez et al.
patent: 5694371 (1997-12-01), Kawaguchi
patent: 5999023 (1999-12-01), Kim
patent: 6040723 (2000-03-01), Sato
patent: 6078202 (2000-06-01), Tomatsuri et al.
Fujioka Shin-ya
Tomita Hiroyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Dinh Paul
Fujitsu Limited
Wells Kenneth B.
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