Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1992-02-03
1992-12-22
Hille, Rolf
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257900, 257903, H01L 2701, H01L 2702, H01L 2904
Patent
active
051737540
ABSTRACT:
An SRAM wafer is conventionally fabricated through the definition of the gate poly. The PMOS oxide is then applied in a layer that uniformly covers the surface and sidewalls of the gate poly, then the interpoly contacts are patterned and etched and the NMOS S/D's are implanted. The PMOS load poly is deposited, again in a layer that uniformly covers the PMOS oxide over the surface and sidewalls of the gate poly. Oxide spacers are formed on the PMOS poly along the gate poly sidewalls, and a P+ implantation forms the PMOS sources and drains. The oxide spacers protect an L-shaped region along the poly gate sidewall from the P+ implant, thus defining PMOS load channels on either side of the gate poly that are gated by the gate poly sidewalls. The foot of the L on one side and the extension of the L above the gate poly on the other create gate/drain offsets that reduce I(off). Optionally, a gate poly/oxide stack may be used to enlarge one of the gate/drain offsets.
REFERENCES:
patent: 4554572 (1985-11-01), Chatterjee
patent: 4724530 (1988-02-01), Dingwall
patent: 4980732 (1990-12-01), Okazawa
patent: 5001540 (1991-03-01), Ishihara
A 0.1 .mu.A Standby Current, Bounding-Noise-Immune 1 Mb SRAM, by Manabu Ando, et al. NEC Corporation, Japan.
Hille Rolf
Limanek Robert
Micro)n Technology, Inc.
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