Patent
1987-03-05
1989-03-28
Kucia, R. R.
357 67, H01L 2354
Patent
active
048168955
ABSTRACT:
A semiconductor device including interconnection lines for connecting element regions is disclosed. Each of interconnection lines is comprised of a first layer consisting essentially of aluminum, an alumina film formed on the first layer and a second layer containing silicon and deposited on the alumina film. Refractory metal silicide such as tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide and chrominum silicide is favorably employed as the second layer. Hillock formation and electromigration are thus prevented or suppressed.
REFERENCES:
patent: 3699011 (1972-10-01), Nishimura
patent: 3702427 (1972-11-01), Learn et al.
patent: 4003772 (1977-01-01), Hanazono et al.
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4190466 (1980-02-01), Bhattacharyya et al.
patent: 4507852 (1985-04-01), Karulkar
patent: 4554572 (1985-11-01), Chatterjee
patent: 4561009 (1985-12-01), Yonezawa et al.
patent: 4566940 (1986-01-01), Itsumi et al.
patent: 4734754 (1988-03-01), Nikawa
Ryoichi Tomoziki, Flattening in Multi-Layer WIRING, SEMICONDUCTOR WORLD, Oct. 1984, pp. 116-120; translation attached in 357/67S.
Kucia R. R.
NEC Corporation
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