Integrated circuit device with a ROM matrix

Details Integrated circuit device with a ROM matrix Integrated circuit device with a ROM matrix

2005-01-18

2009-06-30

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read only systems

C365S205000

Reexamination Certificate

active

07554831

ABSTRACT:
A read only memory matrix in an integrated circuit contains data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells of the matrix. A differential sense amplifier has a first input coupled to a bit line, a second input coupled to a reference circuit and a control input for controlling activation and deactivation of amplification by the sense amplifier. A coupling circuit controllably permits charge sharing between a selectable one of the bit lines and the first input. A timing circuit is arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase. The timing circuit controls the coupling circuit to permit charge sharing between the input and the selectable one of the bit lines in the first phase. In the second phase the timing circuit controls the coupling circuit to prevent charge sharing, makes the reference circuit deactivate driving the reference voltage, and subsequently activates amplification by the differential sense amplifier. Preferably the timing circuit contains a dummy bit line and a trigger circuit for triggering the second phase when a potential swing on the dummy bit line exceeds a threshold value.

REFERENCES:
patent: 4612629 (1986-09-01), Harari
patent: 5461713 (1995-10-01), Pascucci
patent: 5930180 (1999-07-01), Callahan
patent: 6538914 (2003-03-01), Chung
patent: 2003/0218920 (2003-11-01), Harari
patent: 2004/0159870 (2004-08-01), Ishiguro
patent: 0 570 708 (1993-11-01), None
Takahashi O et al: “A 1-GHZ Logic Circuit Family With Sense Amplifiers”; IEEE Journal of Solid-State Circuits; IEEE Inc N.Y. US; vol. 34 No. 5; May 1999; pp. 616-622.

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