Integrated circuit device tester

Details Integrated circuit device tester Integrated circuit device tester

1998-07-08

2000-12-05

Nguyen, Vinh P.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324765, G01R 1900

Patent

active

061572004

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to an integrated circuit device tester for testing semiconductor integrated circuit devices (ICs) or large-scale integrated circuit devices (LSIs).
In FIG. 1 there is shown in block form the general configuration of an integrated circuit device tester in wide use. Reference numeral 100 denotes a test head and 200 a tester main frame. The test head 100 has a performance board 101 and a pin electronics 102 mounted thereon. The performance board 101 has a socket (not shown in particular) for contact with a device under test (hereinafter referred to as a DUT) to establish therethrough electric connections between it and the tester.
The pin electronics 102 has a driver group 103 for electrically driving the DUT, an analog comparator group 104 for checking response output signals read out of the DUT to determine if their H and L logic have normal voltage values, and a relay matrix 105 for switching the device groups that are connected to respective terminals of the DUT.
The tester main frame has a pattern generator 201, from which test pattern data (a digital signal) is output. The test pattern data and a timing edge signal from a timing generator are applied to a formatter 202, by which a pattern signal (a signal having an analog waveform) to be applied to each terminal of the DUT is generated. The pattern signal is provided via a pattern transmission line 301 to the test head 100, wherein it is applied via the driver group 103 to each terminals of the DUT. Incidentally, a timing signal is also contained in the pattern signal that is sent over the pattern transmission line 103.
The comparison results by the analog comparator group 104 are sent via response signal transmission lines 302 back to the tester main frame 200, wherein they are logically compared by a logical comparator 203 with expectation patterns from the pattern generator 201 to detect a mismatch between them and consequently a failing part. Reference numeral 204 denotes a failure memory, in which upon each detection of a mismatch by the logical comparator 203, H or L logic representing a failure is written at an address where the failure occurred.
Reference numeral 205 denotes a timing generator. As regards the timing generator 205, the presence of a coarse delay circuit DY1 and a fine delay circuit DY2 will be described first, for convenience of describing later on that, according to the present invention, they are separately provided in the tester main frame 200 and the test head 100, respectively.
Conventionally, the timing generator 204 frequency-divides a reference clock CLK, shown in FIG. 2, Row A, to obtain a rate pulse RAT (FIG. 2, Row B) that determines the test period or cycle T; besides, the timing generator 204 delays the rate pulse RAT by arbitrary time intervals to generate various timing signals such as the rise and fall timing of the test pattern signal waveform, the strobe timing of the analog comparator group 104 and the timing for the comparing operation of the logic comparator 203.
Accordingly, the timing generator 202 has a number of delay circuits by which the rate pulse RATE can be delayed for arbitrary periods of time within the range of the test period T or within a several-fold range; these delay circuits are used to generate various timing signals which are delayed behind the reference timing by arbitrary time intervals, such as timing signals T1 and T2 shown in FIG. 2, Rows C and D.
These delay circuits in the timing generator 205 are formed by combinations of coarse delay circuits DY1 each of which counts the clock pulses CLK and provides a delay time in units of the period .tau.1 of the clock CLK and fine delay circuits DY2 each of which subdivides the range of the period .tau.1 of the clock CLK to define a delay time; these delay circuits define the rise and fall timing of the test pattern signal by resolution on the order of picoseconds, for instance.
The tester main frame 200 further includes a DC test unit 206, a load test unit 207, a first reference volta

REFERENCES:
patent: 4517512 (1985-05-01), Petrich et al.
patent: 4875006 (1989-10-01), Henley et al.
patent: 5095262 (1992-03-01), Henley et al.
patent: 5477139 (1995-12-01), West et al.
patent: 5946250 (1999-08-01), Suzuki

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