Integrated circuit device structure including foamed...

Details Integrated circuit device structure including foamed... Integrated circuit device structure including foamed...

2000-01-10

2004-05-11

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

Reexamination Certificate

active

06734562

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the present invention relates to insulation materials of an integrated circuit.
BACKGROUND OF THE INVENTION
To meet demands for faster processors and higher capacity memories, integrated circuit (IC) designers are focusing on decreasing the minimum feature size within ICs. By minimizing the feature size within an IC, device density on an individual chip increases exponentially, as desired, enabling designers to meet the demands imposed on them. As the minimum feature size in semiconductor ICs decreases, however, capacitive coupling between adjacent conductive layers is becoming problematic. In particular, for example, capacitive coupling between metal lines in the metallization level of ICs limits the minimum feature size that is operatively achievable.
One attempt to minimize the problem of capacitive coupling between metal lines involves utilizing a relatively low dielectric constant material to insulate the metal lines. Conventionally, silicon dioxide (SiO
2
), having a dielectric constant of about 4.0∈
o
(wherein ∈
o
is the permittivity of space), is used as the insulating material in ICs. To date, the minimum dielectric constant possible, however, is that of air, the dielectric constant being 1.0∈
o
. Nevertheless, the use of air as an insulating material, such as provided using an air bridge, has drawbacks. For example, IC structures utilizing air insulation lack mechanical strength and protection from their environment.
SiO
2
and air have been utilized together in an inorganic, porous silica xerogel film in order to incorporate both the mechanical strength of SiO
2
and the low dielectric constant of air. In this manner, SiO
2
behaves as a matrix for porous structures containing air. However, porous silica xerogel film has a tendency to absorb water during processing. The water absorbed during processing is released during aging, resulting in cracking and a pulling away of the porous silica xerogel film from the substrate on which it is applied.
Even when nonporous SiO
2
is utilized, as the minimum feature size within an IC decreases, significant stress develops at the interface between the SiO
2
and metal on which SiO
2
is commonly formed, causing potentially detrimental disruptions in the electrical performance of the IC. For example, the stress may be great enough to rupture a metal line adjacent to the SiO
2
insulating layer. Such stress develops from the large difference in the coefficient of thermal expansion between that of SiO
2
and that of the metal. The coefficient of thermal expansion of SiO
2
is about 0.5 &mgr;m/m° C. to about 3.0 &mgr;m/m° C. The coefficient of thermal expansion of Type 295.0 aluminum, an alloy similar in composition to the aluminum alloys commonly used in the metallization level of an IC, is about 23 &mgr;m/m° C. The coefficient of thermal expansion for aluminum is significantly higher than that of SiO
2
. Likewise, the coefficient of thermal expansion of Type C81100 copper, an alloy similar in composition to a copper alloy which may also be used in integrated circuit metallization layers, is about 16.9 &mgr;m/m° C., also significantly higher than that of SiO
2
. The metallization layer's larger coefficient of thermal expansion results in its absorption of all of the strain caused by the large difference in the coefficients of thermal expansion upon heating and cooling. The result of such strain absorption is that the metallization layer is placed in tension and the SiO
2
layer is placed under slight compression. The high compressive yield strength of SiO
2
prevents its rupture. In contrast, the relatively low tensile yield strength of the metallization layer promotes its rupture, leading to integrated circuit failure.
It has also been reported that certain polymeric materials have dielectric constants less than that of SiO
2
. For example, polyimides are known to have a dielectric constant of about 2.8∈
o
to about 3.5∈
o
. The use of polyimides in the metallization level of ICs is well known. For example, Carey (U.S. Pat. No. 5,173,442) reported the use of a polyimide as an interlayer dielectric.
Others have reported that foaming (i.e., introducing air into) polymeric material results in a material having a dielectric constant of about 1.2∈
o
to about 1.8∈
o
. One such foaming process is described by Cha et al. (U.S. Pat. No. 5,158,986). The exact dielectric constant of such foamed polymers depends on the percentage of voids (i.e., air) present and the dielectric constant of the polymeric material that was foamed. The use of such foamed polymers, however, has been limited to electronic packaging applications and multichip module applications for microwave substrates. Multichip module processing is not suitable for use in semiconductor fabrication because in multichip module processing, a metal insulator “sandwich” is formed as a unit and is then applied to a surface. Due to the oftentimes uneven topographies at the metallization level of an IC, each of the metal layer and the insulation layer need to be formed separately, allowing them to conform to the underlying topography.
Therefore, there is a need for an insulating material for use in an integrated circuit that has adequate mechanical integrity, as well as a relatively low dielectric constant. The capacitive coupling problem between conductive layers needs to be minimized as device density continues to increase within an integrated circuit.
SUMMARY OF THE INVENTION
A method of forming an insulating material for use in an integrated circuit in accordance with the present invention includes providing a substrate of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material.
In one embodiment of the method, the step of converting the polymeric material comprises exposing at least a portion of the polymeric material to a supercritical fluid. Preferably, the supercritical fluid is carbon dioxide.
In another embodiment of the method, the step of converting the polymeric material includes converting at least a portion of the polymeric material to a foamed polymeric material having a maximum cell size of less than about 3.0 microns, a cell size of less than about 1.0 micron, and even a maximum cell size of less than about 0.1 micron.
Further, a method of fabricating an interconnect for an integrated circuit in accordance with the present invention is described. The method includes providing a substrate that includes an active area of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material and at least one contact hole is defined in the foamed polymeric material to the active area of the integrated circuit. The contact hole is then filled with a conductive material. In much the same manner, a method of fabricating a via in the foamed polymeric material is described.
In such various methods, the polymeric material on the substrate may be an organic polymer, an organic oligomer, and an organic monomer. Preferably, the polymeric material on the substrate is an organic polymer selected from the group of a polyimide, a fluorinated polymer, and a parylene. More preferably the polymeric material includes a polymeric material selected from the group of Type I polyimide, Type III polyimide, and Type V polyimide, or the polymeric material is a fluorinated polyimide. Most preferably, the polymeric material includes a Type I polyimide or a fluorinated Type I polyimide.
Further in accordance with the present invention, an integrated circuit is described which includes a substrate of the integrated circuit and a foamed polymeric material on at least a portion of the substrate. In various embodiments, the integrated circuit further includes a conductive layer adjacent the foamed polymeric material. The conductive layer may be a metal

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