Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2001-06-28
2002-11-05
Martin, David (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S792000, C361S790000, C361S764000, C361S777000, C174S250000, C174S255000, C439S066000
Reexamination Certificate
active
06477058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit device packaging. More particularly, the present invention relates to integrated circuit device packages comprising multiple, stacked components that are electrically interconnected using land grid array connection techniques.
2. Description of the Related Art
To provide a higher level of functionality to an integrated circuit (IC) device, the device can be mounted on a circuit board, for example, a daughter card, carrying function enhancing electrical elements. The daughter card is in turn electrically connected to a larger circuit board, usually the mother board of a computer.
The terminations on the IC device are typically soldered to pads on the daughter card. However, high pin count devices, such as very large scale integrated (VLSI) ICs, that are soldered in place are difficult to rework in the event of a faulty connection nor can they be easily removed and replaced if found to be defective, or in need of upgrading. If there are other expensive components on the daughter card, the scrap cost can be significant if the rework or removal operation fails. In addition, soldered joints are often unreliable under temperature cycling and perform poorly under the compressive loads imposed by heat sinks required to dissipate heat from high power IC devices.
Another approach to connecting an IC device to a daughter card is to use mating pins and pin sockets, such as pin grid arrays. However, such connectors add cost to the components and often cause signal degradation because of increased inductance.
The connection of the daughter card to the mother board has also involved the use of hard wiring, mateable pins and pin sockets, as well as other interconnections such as edge connectors. Here again, high pin or lead counts make such connections undesirable for the reasons already stated: high cost, signal degradation and, where soldered joints are utilized, the difficulty of repair or replacement.
In one known area array IC device packaging and interconnection technique, called land grid array (LGA), electrical connection is established through pad-to-pad contact by clamping the IC device to a higher assembly through an intervening LGA interposer socket having compliant, coplanarity-maintaining contacts. LGA technology provides high density, small footprint, low profile IC device interconnections with low inductance for high speed applications. Moreover, LGA devices avoid thermal mismatch problems, cost less to manufacture and to assemble and can be easily removed and replaced.
U.S. Pat. No. 5,883,788 to Ondricek, et al., for BACKING PLATE FOR LGA MOUNTING OF INTEGRATED CIRCUITS
FACILITATES PROBING OF THE IC'S PINS; U.S. Pat. No. 6,061,235 to Cromwell, et al., for METHOD AND APPARATUS FOR A MODULAR INTEGRATED APPARATUS FOR HEAT DISSIPATION, PROCESSOR INTEGRATION, ELECTRICAL INTERFACE, AND ELECTROMAGNETIC INTERFERENCE MANAGEMENT; U.S. Pat. No. 6,084,178 to Cromwell for PERIMETER CLAMP FOR MOUNTING AND ALIGNING A SEMICONDUCTOR COMPONENT AS PART OF A FIELD REPLACEMENT UNIT (FRU); U.S. Pat. No. 6,198,630 to Cromwell for METHOD AND APPARATUS FOR ELECTRICAL AND MECHANICAL ATTACHMENT, AND ELECTROMAGNETIC INTERFERENCE AND THERMAL MANAGEMENT OF HIGH SPEED, HIGH DENSITY VLSI MODULES; and U.S. Pat. No. 6,219,239 to Mellberg, et al., for EMI REDUCTION DEVICE AND ASSEMBLY, all of which are commonly assigned to the assignee of the present invention, disclose examples of LGA IC device packaging. These patents are incorporated herein by reference for their teachings of LGA interconnection and clamping techniques, and integrated thermal management.
SUMMARY OF THE INVENTION
In accordance with one specific, exemplary embodiment of the invention, there is provided an integrated circuit device package comprising a first land grid array (LGA) interposer socket positioned between, and in communication with, an LGA integrated circuit device and a first side of a first circuit board; a second LGA interposer socket positioned between, and in communication with, a second circuit board and a second side of the first circuit board, wherein the second side of the first circuit board is opposite to and parallel with the first side of the first circuit board; and a clamping mechanism for compressively urging together the LGA integrated circuit device, the first LGA interposer socket, the first circuit board, the second LGA interposer socket, and the second circuit board into electrical interconnection under a predetermined load.
In accordance with another specific, exemplary embodiment of the invention, there is provided an integrated circuit device package comprising a land grid array integrated circuit device; a first circuit board having opposed, parallel, first and second major surfaces, each of the major surfaces of the first circuit board including a land grid array; a second circuit board having opposed, parallel, first and second major surfaces, the first major surface of the second circuit board including a land grid array; a first land grid array interposer socket sandwiched between the land grid array integrated circuit device and the land grid array on the first major surface of the first circuit board; a second land grid array interposer socket sandwiched between the land grid array on the second major surface of the first circuit board and the land grid array on the first major surface of the second circuit board; and a clamping mechanism for compressively urging into electrical interconnection (i) the land grid array integrated circuit device and the land grid array on the first major surface of the first circuit board through the first land grid array interposer socket, and (ii) the land grid array on the second major surface of the first circuit board and the land grid array on the first major surface of the second circuit board through the second land grid array interposer socket.
In accordance with yet another specific, exemplary embodiment of the invention, there is provided an apparatus for electrically interconnecting a plurality of stacked electrical components including a land grid array integrated circuit device, a daughter card and a mother board, the daughter card having opposed, parallel, first and second major surfaces, the mother board having opposed, parallel, first and second major surfaces, the apparatus comprising a land grid array on each of the first and second major surfaces of the daughter board electrically connected to electrical elements carried by the daughter board; a land grid array on the; first major surface of the mother board electrically connected to electrical elements carried by the mother board; a first land grid array interposer socket and a second land grid array interposer socket, the first interposer socket enabling electrical connection between the land grid array integrated circuit device and the land grid array on the first major surface of the daughter card, and the second land grid array interposer socket enabling electrical connection between the land grid array on the second major surface of the daughter card and the land grid array on the mother board; a clamping plate for overlying the integrated circuit device; and a clamping mechanism for compressively urging the integrated circuit device, the first interposer socket, the daughter card, the second interposer socket and the mother board into electrical interconnection under a predetermined load.
REFERENCES:
patent: 5215472 (1993-06-01), DelPrete et al.
patent: 5329426 (1994-07-01), Villani
patent: 5883788 (1999-03-01), Ondricek et al.
patent: 6061235 (2000-05-01), Cromwell et al.
patent: 6074219 (2000-06-01), Tustaniwskyj et al.
patent: 6084178 (2000-07-01), Cromwell
patent: 6094344 (2000-07-01), Nakagawa et al.
patent: 6198630 (2001-03-01), Cromwell
patent: 6219239 (2001-04-01), Mellberg et al.
patent: 6287892 (2001-09-01), Takahashi et al.
Craig Jonathan W
Deeney Jeffrey L.
Luebs Richard J
Peters David W.
Bui Hung
Martin David
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