Integrated circuit device manufacture

Details Integrated circuit device manufacture Integrated circuit device manufacture

1999-02-05

2001-10-09

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S014000, C438S107000, C438S455000

Reexamination Certificate

active

06300149

ABSTRACT:

The present invention relates to a method of manufacture of an integrated circuit device such as a memory device of the semiconductor type, together with the resultant product thereof.
In recent years large advances have been made in the area of integrated circuit and semiconductor memory device manufacture, resulting in the widespread availability of devices of ever increasing capacity and ever reducing cost. There are, however, significant problems associated with such device manufacture. Currently available semiconductor memory devices, for example, can have in the region of 100×10
6
individual elements contained within them. The control of such devices requires that each of these elements to work. With each element having sub-micron dimensions, the possibility of having a manufacturing error is substantial. One defect, unwanted dust particle, or miss-aligned region can result in the production of a worthless device. This means that, as individual element size drops and the number of elements increases, the yield from the manufacturing process either drops exponentially or there must be exponential improvements in manufacturing process control. This has led to a significant increase in the cost of semiconductor memory device fabrication facilities.
A further disadvantage with the processes involved in the manufacture of current integrated circuit devices is that such devices must be formed from elements which are formed on a single substrate and in a single plane. This means that it is not possible to stack more than a few layers individual elements, and that the dimensions of the device must be increased in the single plane if overall device capacity is to be increased.
The present invention seeks to provide a solution to the above problems.
According to the present invention there is provided a method of manufacturing an integrated circuit device from a plurality of physically separate individual electrical elements, the method comprising the steps of:
manufacturing each of said plurality of elements;
verifying the operability of each of said elements and discarding inoperable elements;
retaining the operable elements;
aligning the retained elements so that each element is adjacent to at least one other element; and
treating the arrangement of elements to provide connections therebetween and thereby to produce a single integrated circuit device.
The elements may be retained in a fluid.
The treatment may involve drying the arrangement of elements to remove any retained fluid. The treatment step may then involve the further steps heating and then cooling of the elements to melt electrical contacts formed thereon to bring them into engagement with electrical contacts on adjacent elements. An alternative is to place the arranged elements in a chemical plating solution to increase the metal volume until they make contact with each other or a patterned substrate. A further alternative is to remove a surface coating formed on the elements to enable direct electrical contact. In a preferred embodiment, each of the elements is formed with a width less than 1 micron for three dimensional alignment, although in two dimensional alignment larger elements can be used.
The elements may be formed from semiconductor material, and may be memory elements, forming, as a result, in a semiconductor device.
The elements may be aligned in a single plane or in a stacked arrangement. The alignment may constitute two steps, an initial alignment of elements into a lattice, followed by directional alignment of the elements, or directional alignment followed by alignment into a lattice. The lattice alignment may be performed by employment of magnetic or electrostatic forces or by employment of colloidal chemistry techniques. Each of the plurality of elements may be formed so that is has a symmetrical shape to ensure ease of alignment. This may require each element to have some redundant features.
The fluid may be a de-ionized solution. The lattice alignment may be performed by increasing the concentration of elements held in the fluid until the elements align in a periodic crystal-like structure, which may be a high entropy structure. With this approach, the elements may need to be coated to overcome Van Der Waals forces, and the coating may provide the elements with charged surfaces.
The elements may be formed so that they are polarised or coated in order to ensure mutual attraction, or are magnetically attracted to one another or so that they are aligned by an external magnetic or electric field so that directional alignment can be performed.
The present invention also provides a device produced by the above method.


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