Integrated-circuit device isolation

Details Integrated-circuit device isolation Integrated-circuit device isolation

1989-10-19

1991-03-26

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 72, H01L2176

Patent

active

050028987

ABSTRACT:
In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.

REFERENCES:
patent: 4407696 (1983-10-01), Han et al.
patent: 4541167 (1985-09-01), Havemann et al.
patent: 4630356 (1986-12-01), Christie et al.
patent: 4746625 (1988-05-01), Morita et al.
N. Hoshi et al., "An Improved LOCOS Technology Using Thin Oxide and Polysilicon Buffer Layers", Journal of the Electrochemical Society of Japan, vol. 98 (1984), pp. 78-83.

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