Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...
Reexamination Certificate
2000-02-24
2002-05-07
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With contact or metallization configuration to reduce...
C257S203000, C257S207000, C257S208000, C257S459000
Reexamination Certificate
active
06384464
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices, and more particularly to pads for integrated circuit devices.
BACKGROUND OF THE INVENTION
As integrated circuit devices become more highly integrated, it may become increasingly important to planarize the interlayer dielectric layers thereof. As is well known to those having skill in the art, integrated circuit devices generally include multiple levels of conductive wiring layers, for example, metallization, that are separated by interlayer dielectric layers. As the number of wiring layers and/or the density thereof continue to increase, it may become increasingly difficult to planarize the interlayer dielectric layers. As is well known to those having skill in the art, when the interlayer dielectric layers become nonplanar, it may be difficult to form subsequent wiring layers thereon, because the depth of focus may vary during photolithography. In a worst case scenario, portions of the wiring pattern may be open circuited and/or adjacent portions may be short circuited. As is also well known to those having skill in the art, planarization of the interlayer dielectric layer may take place using thermal reflow, chemical mechanical polishing and/or other conventional planarization techniques.
It also is known that planarization may be greatly affected by the pattern density of an underlying wiring layer. Accordingly, it is known to add a dummy pattern between the real patterns of an underlying wiring layer in order to make the pattern density more uniform.
FIGS. 1-3
illustrate an embodiment of an integrated circuit device in which dummy patterns have been added to make a wiring layer more uniform. In particular,
FIG. 1
is a top view of an integrated circuit device in which a dummy pattern is formed between a real pattern and a pad.
FIG. 2
is a cross-sectional view taken along the line II—II of FIG.
1
.
FIG. 3
is an enlarged top view of
FIG. 1
, illustrating bridges that may be generated between the dummy pattern and the pads, thereby causing a short circuit.
More specifically, as shown in
FIGS. 1 and 2
, a real pattern
1
is formed from a conductive layer, such as a metal layer, on a surface of an integrated circuit substrate, such as a semiconductor substrate
10
that includes one or more dielectric layers thereon. Pads
3
also are formed from the conductive layer. A dummy pattern
5
also is formed between the pads
3
and the real pattern
1
, in order to make the pattern density more uniform. A plurality of apertures
7
also may be formed in the dummy pattern
5
in order to reduce stress therein. A plurality of grooves
9
also is formed between the real pattern
1
and the dummy pattern
5
, and between the pads
3
and the dummy pattern
5
. The groove
9
can prevent formation of bridges between the real pattern
1
and the dummy pattern
5
, and between the pads
3
and the dummy pattern
5
.
Unfortunately, as shown in
FIG. 3
, notwithstanding the provision of the grooves
9
, a short circuit may be generated between a pad
3
and a second pad
3
′ due to bridges
11
that are formed between the pad
3
and the dummy pattern
5
, and the second pad
3
′ and the dummy pattern
5
. These bridges may be formed during electrical tests after forming the real pattern
1
and the pads
3
. In order to solve this problem, the distance between a pad
3
and the dummy pattern
5
may be increased, for example, by increasing the size of the grooves
9
. Unfortunately, when the grooves
9
are increased in size, planarization may be adversely impacted.
SUMMARY OF THE INVENTION
The present invention can prevent short circuits between a plurality of pads on the surface of an integrated circuit substrate and a first dummy pattern on the surface that is spaced apart from and surrounds the plurality of pads, while still allowing planarity of a dielectric layer that is subsequently formed thereon to be retained. In preferred embodiments, a second dummy pattern is provided on the surface between the plurality of pads and the first dummy pattern, which is spaced apart from the plurality of pads and from the first dummy pattern, and that surrounds the plurality of pads. The second dummy pattern preferably comprises a plurality of rings on the surface, a respective one of which is between a respective one of the plurality of pads and the first dummy pattern and surrounds the respective one of the plurality of pads. The rings may be of circular, polygonal and/or other shape. By providing the second dummy pattern, it is possible to prevent short circuits between the pads and the first dummy patterns because the second dummy pattern allows the first dummy pattern to be spaced further apart from the plurality of pads. Moreover, by interposing the second dummy pattern between the plurality of pads and the first dummy pattern, planarity of subsequently formed dielectric layers still can be maintained.
In other embodiments of the present invention, the second dummy pattern comprises a plurality of concentric dummy subpatterns, such as subrings, on the surface between the plurality of pads and the first dummy patterns, that are spaced apart from the plurality of pads, from one another and from the first dummy pattern, and that surround the plurality of pads. A real pattern also may be provided on the surface, wherein the first dummy pattern is spaced apart from and surrounds the real pattern.
In preferred embodiments, the second dummy pattern is spaced apart from the plurality of pads and from the first dummy pattern by distances that are between about 0.5 &mgr;m and about 10 &mgr;m. In other embodiments, a first groove pattern also may be included between the plurality of pads and the second dummy pattern and a second groove pattern also may be included between the second dummy pattern and the first dummy pattern. Accordingly, short circuits may be prevented between the plurality of pads and the first dummy pattern, while retaining planarity.
REFERENCES:
patent: 4746966 (1988-05-01), Fitzgerald et al.
patent: 5534726 (1996-07-01), Ohoka
patent: 5-226339 (1993-09-01), None
patent: 05226339 (1993-09-01), None
English translation, Notice to Submit Response, Korean App. 99-8765, Feb. 12, 2001.
Flynn Nathan
Wilson Scott R.
LandOfFree
Integrated circuit device including dummy patterns... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit device including dummy patterns..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit device including dummy patterns... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2854613