Integrated circuit device having vertical MOS provided with Zene

Details Integrated circuit device having vertical MOS provided with Zene Integrated circuit device having vertical MOS provided with Zene

1987-06-17

1989-08-29

James, Andrew J.

357 52, 357 13, 357 42, H01L 2978

Patent

active

048622338

ABSTRACT:
Vertical MOS and another component such as CMOS are made in a single semiconductor substrate having a highly doped underlying layer and a lightly doped epitaxial surface layer of a first conductivity type. The vertical MOS includes a channel region of a second conductivity type, formed in the surface layer, and a source region of the first conductivity type, formed in the channel region. The channel region is made deep and joined with the highly doped underlying layer to form a first Zener diode for regulating a drain-source voltage. A drain electrode is formed on the bottom surface of the substrate and connected to a power supply, and a topside source electrode is connected to a load. The vertical MOS is surrounded, and separated from the CMOS, by a grounded guard ring region of the second conductivity type, formed in the surface layer. The guard ring region is also made deep and joined with the underlying layer.

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Kyomasu et al., "Analysis of Latch-Up in CMOS IC," Denshi Tsushin Gakkai Ronbunshi, '78/2, vol. J61-CN02, pp. 106-113.
ISSCC 86/Weds., 2/19/86, International Solid-State Circuits Conference, Einzinger et al., pp. 22-23 and 289, (Session I, Analog Techniques).
IEEE, Power Electronics Specialists Conference Record, '85, The Design of a High Power Solid State Automotive Switch in CMOS-VDMOS Technology, Wrathall, 229-233.

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