Integrated circuit device having tristate input buffer for reduc

Details Integrated circuit device having tristate input buffer for reduc Integrated circuit device having tristate input buffer for reduc

1992-12-21

1994-03-01

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307473, H03K 1700

Patent

active

052910806

ABSTRACT:
A large scale integrated circuit device includes a plurality of internal devices, an address decoding circuit, a bus control circuit, a first tristate buffer, and an output buffer. The internal devices are connected to an internal data bus and selectively perform data input/output operations. The address decoding circuit decodes an address signal from an address bus of a system to deliver an internal device select signal to one of the internal devices and an internal device select indication signal indicating that one of the internal devices is selected. The bus control circuit delivers an output control signal and an input control signal upon receiving the internal device select indication signal and one of a data write signal and a data read signal. The first tristate buffer controls data input to the internal data bus in accordance with the input control signal. The output buffer controls data output from the internal data bus in accordance with the output control signal.

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patent: 5107148 (1992-04-01), Millman
patent: 5193204 (1993-03-01), Qureshi et al.
patent: 5214330 (1993-05-01), Okazaki

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