Multiplex communications – Duplex
Patent
1997-01-13
1999-04-27
Holloway, III, Edwin C.
Multiplex communications
Duplex
34082586, 364490, 257210, 257499, 395871, 326 17, 370537, H01L 2900
Patent
active
058986774
ABSTRACT:
Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area. One aspect of the invention is directed to using auto-routing switching techniques for combining signals. Another aspect is directed to applying these combining/expanding techniques to the integrated circuit design process.
REFERENCES:
patent: 3555195 (1971-01-01), Rester et al.
patent: 3573740 (1971-04-01), Berger et al.
patent: 4396980 (1983-08-01), Hingarh
patent: 4639620 (1987-01-01), Wagenmakers
patent: 4755765 (1988-07-01), Ferland
patent: 4855999 (1989-08-01), Chao
patent: 4884264 (1989-11-01), Servel et al.
patent: 4939729 (1990-07-01), Weisser
patent: 5012126 (1991-04-01), Feldbaumer et al.
patent: 5233603 (1993-08-01), Takeuchi et al.
patent: 5237184 (1993-08-01), Yonemary et al.
patent: 5237564 (1993-08-01), Lespagno et al.
patent: 5341309 (1994-08-01), Kawata
patent: 5359212 (1994-10-01), Kudou et al.
patent: 5475680 (1995-12-01), Turner
patent: 5495422 (1996-02-01), Olson
patent: 5615126 (1997-03-01), Deeley et al.
patent: 5625563 (1997-04-01), Rostoker et al.
Dangelo Carlos
Deeley Richard
Holloway III Edwin C.
LSI Logic Corporation
Wilson Jr. William H.
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