Integrated circuit device having a geometry to enhance fabricati

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257786, 257676, 257773, 437180, 437209, H01L 2702

Patent

active

053192249

ABSTRACT:
A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substrate (10, 20). Next, circuits (12, 22) having different signal processing functions respectively are formed in regions of the substrates (10, 20) not occupied by the bonding pads (11, 21), and then, input/output terminals of the circuits (12, 22) are interconnected to respective ones of the bonding pads (11, 21). According to such a manufacturing method of integrated circuit devices, it is possible to employ common devices for wafer test and the same packages for incorporating, and thus reduce production cost and development cost, in case of small quantity production of various types.

REFERENCES:
patent: 3495133 (1970-02-01), Miller
patent: 3795845 (1974-03-01), Cass et al.
patent: 4080512 (1978-03-01), Ramet et al.
patent: 4746966 (1988-05-01), Fitzgerald et al.
patent: 4831433 (1989-05-01), Ogura
patent: 4839820 (1989-06-01), Kinoshita et al.
patent: 4864381 (1989-09-01), Seefeldt et al.
patent: 5017993 (1991-05-01), Shibata
patent: 5021856 (1991-06-01), Wheaton
patent: 5109265 (1992-04-01), Utesch et al.
"Chip I/O Macros Growable and Placeable Within Cell Array", IBM Technical Disclosure Bulletin, vol. 30, No. 10, Mar., 1988, pp. 222-223.
"Large Chip Substrate", IBM Technical Disclosure Bulletin, vol. 28, No. 3, Aug., 1985, p. 965.
Mitsutaka Sato, "Plastic-Molded Semiconductor Device and its Manufacture", Patent Abstracts of Japan, E-832, Oct. 17, 1989, vol. 13, No. 459 (Corresponds to JP 1-179351).
A. H. Mones et al., "Interconnecting and Packaging VLsI Chips", Solid-State Technology, Jan., 1984, pp. 119-122.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated circuit device having a geometry to enhance fabricati does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit device having a geometry to enhance fabricati, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit device having a geometry to enhance fabricati will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-794835

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.