Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-08-31
2003-11-18
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S501000, C324S765010
Reexamination Certificate
active
06650130
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to apparatus and methods for inspecting integrated circuit devices, and in particular to such apparatus and methods for detecting defects in integrated circuit devices by imaging light emissions therefrom.
BACKGROUND OF THE INVENTION
Detecting defective integrated circuit devices (“chips”) on a wafer early in the semiconductor manufacturing process saves significant time and money in subsequent processing and testing. Currently, defects are detected in a variety of ways, including burn -in, voltage screen and IDDq (i.e., quiescent current) testing. Performing these tests at wafer level requires individually probing each chip, applying input signals and measuring the corresponding output signals.
Further, in the case of IDDq testing, current readings are imperfect indicators of the presence of random defects, primarily for two reasons. The first reason is that current readings give no indication of whether any excess current is distributed throughout the chip or confined to one or more specific locations. While most defect types will cause an elevated current, an elevated current is not necessarily indicative of defects. Hence, with the present techniques for measuring current, there is the risk of scrapping otherwise good chips. The second reason is that current thresholds are imprecise. If set too low, good chips may be scrapped. If set too high, defective chips may remain undetected.
Numerous industry studies have shown that a very high percentage of defects in chips result in elevated quiescent power supply current. Further studies and failure analysis results indicate that this current generates photon emission and/or localized thermal emission (i.e., joule heating caused by IDDq-driven power dissipation) for a large majority of chip defects. Thus, an area of abnormal light emission or heat dissipation on a fully static CMOS part in a quiescent state, would confirm the presence of a manufacturing defect or design error.
Accordingly, techniques have been developed wherein light emitted from areas on a defective chip is imaged and analyzed to deduce the location of the defects. For example, U.S. Pat. No. 4,680,635, U.S. Pat. No. 4,755,874 and U.S. Pat. No. 5,783,835 each disclose an emission microscope for viewing the electro-luminescent emissions of a silicon (i.e., semiconductor) device.
SUMMARY OF THE INVENTION
However, each of these microscopes is only capable of imaging a single chip or a small region therein. More generally, the prior art fails to teach or suggest an apparatus or method of imaging a plurality of chips on a semiconductor wafer so that analysis of defects is performed over substantially the entire wafer simultaneously.
The present invention pertains to apparatus and methods for inspecting integrated circuits, and in particular to such apparatus and methods for detecting defects in integrated circuits by imaging light emissions therefrom.
A first aspect of the invention is a method of detecting one or more defects in a plurality of chips on a wafer. The method comprises the steps of first, simultaneously providing electrical power to the plurality of chips, thereby generating one or more light signals corresponding to one or more defects in the plurality of chips. The next step is simultaneously forming an image of the plurality of chips so as to simultaneously detect the one or more light signals.
A second aspect of the invention is the method as described above, wherein the image of the plurality of chips is formed on a detection surface, and the image is processed so as to identify which chips in the plurality of chips contain the one or more defects. The latter step is preferably accomplished by one of two methods of image processing, discussed in detail below.
A third aspect of the invention is an apparatus for identifying one or more defects in a plurality of chips on a wafer. The apparatus comprises a test head having electrical probes for providing electrical power to the plurality of chips, and a detector to detect one or more light signals emitted by the plurality of chips in response to the electrical power (e.g., current) interacting with a one or more chip defects. The apparatus further includes an imaging system arranged so as to form an image of the plurality of chips, including the light signals corresponding to the defects, onto the detector.
A fourth aspect of the invention is the apparatus as described above, and further including an image processing unit electrically connected to the detector, and an output device electrically connected to the image processing unit, for outputting information from the image processing unit pertaining to the chip defects.
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Kash Jeffrey A.
Nigh Phillip J.
Vallet David P.
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Karlsen Ernest
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