Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2002-03-01
2004-09-21
Whitmore, Stacy A. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257SE23151, C716S030000, C716S030000, C365S063000, C365S072000
Reexamination Certificate
active
06794674
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a wiring structure in an integrated circuit device and to a method for forming the same. More particularly, it relates to a method for optimizing an amount of voltage drop in wiring.
In an integrated circuit represented by a digital circuit, logic gates including an AND gate and a NOR gate are used as elements for composing the circuit. A unit for organizing the logic gates into the circuit is termed a cell. In the digital circuit, cells having different functions in accordance with the types of the logic gates are prepared. By combining the different types of cells, the whole digital circuit acquires a necessary function.
In a typical digital circuit, a ground wiring layer and a power supply wiring layer are provided over a region in which a large number of cells are placed. The cells are arranged laterally such that the respective power supply lines of the cells are connected to each other and that the respective ground lines thereof are connected to each other. Hereinafter, a group of cells arranged laterally will be termed a cell raw.
The cells contain electronic elements required to compose the circuit, e.g., MOS transistors as components. For example, a CMOS inverter circuit contains a PMOS transistor and an NMOS transistor and has a power supply terminal connected to the power supply line of the cell, while having a ground terminal connected to the ground line of the cell. It is to be noted that a circuit in the present specification indicates a portion obtained by connecting electronic elements with a wire (in a broad sense) and does not indicate a closed circuit (in a narrow sense). For example, a CMOS inverter circuit indicates a circuit having a power supply terminal and a ground terminal which are not connected to the power supply line and the ground line, respectively.
FIG. 10
is a plan view showing the respective structures of a cell placement region, power supply lines, and ground lines in a conventional digital circuit composed of cells. As shown in the drawing, a plurality of cell rows
105
x
are aligned vertically in the cell placement region. Each of the cell rows is composed of a plurality of cells
105
arranged laterally. The cell placement region is defined by trunk power supply lines
107
a
and trunk ground lines
107
b
each extending vertically and by branch power supply lines
108
a
and branch ground lines
108
b
each extending laterally. Power supply voltages and ground voltages are supplied from the trunk power supply lines
107
a
and the trunk ground lines
107
b
on both sides of the cell placement region to the individual cells
105
via element power supply lines
106
a
and element ground lines
106
b
. The trunk power supply lines
107
a
and the trunk ground lines
107
b
are connected to the branch power supply lines
108
a
and the branch ground lines
108
b
via through-hole connecting terminals
109
a
-
1
and
109
b
-
1
, respectively. In a cross-sectional structure of a semiconductor integrated circuit device, individual wiring layers are insulated by interlayer insulating films, though they are not shown in
FIG. 10
, and conductor members filled in through holes formed by opening the interlayer insulating films are termed the through-hole connecting terminals.
In the present specification, the power supply lines and the ground lines are generally termed “voltage supply lines”.
The element power supply lines
106
a
, the element ground lines
106
b
, the branch power supply lines
108
a
, and the branch grounded lines
108
b
each extending laterally in
FIG. 10
are provided in a certain wiring layer. On the other hand, the trunk power supply lines
107
a
and the trunk ground lines
107
b
are provided in another wiring layer. The semiconductor integrated circuit device is provided on a semiconductor chip having power supply pads and ground pads to be connected to the branch power supply lines
108
a
and the branch ground lines
108
b
, respectively. The power supply pads and the ground pads are provided in the uppermost layer of the semiconductor chip so that the semiconductor integrated circuit device is electrically connectable to a power supply line and to a ground supply line each external of the semiconductor chip via the power supply pads and the ground pads.
Thus, in the state shown in a plan view, the element power supply lines
106
a
and the element ground lines
106
b
provided in the same wiring layer and extending laterally intersect the trunk power supply lines
107
a
and the trunk ground lines
107
b
provided in the other wiring layer and extending vertically. At the points of intersection of the power supply lines
106
a
and the trunk power supply lines
107
a
, the power supply lines
106
a
and the trunk power supply lines
107
a
are connected to each other via through-hole connecting terminals
109
a
-
2
. On the other hand, the ground lines
106
b
and the trunk ground lines
107
b
are connected to each other via through-hole connecting terminals
109
b
-
2
at the points of intersection of the ground lines
106
b
and the trunk ground lines
107
b.
Thus, each of the wiring layer is internally provided with the plurality of lines extending in a specified direction. Since the through-hole connecting terminals are provided as required at the points of intersection of the lines contained in the different wiring layers, lines other than those shown in
FIG. 10
should be placed with consideration. When signal lines, e.g., are placed in the individual wiring layers, the signal lines should be placed while avoiding the points of intersection.
However, the wiring structure in the conventional semiconductor integrated circuit device has the following drawbacks.
In the conventional structure, the points of intersection restrict the flexibility with which the signal lines are placed. It will be understood that the area allocated to the signal lines is reduced by the points of intersection. Moreover, the branch power supply lines
108
a
and the branch ground lines
108
b
are provided in the same wiring layer (first wiring layer) and the element power supply lines
106
a
of the cells and the element ground lines
106
b
thereof are also provided in the same wiring layer (first wiring layer). As a result, the cell rows
105
x
cannot be placed immediately below the branch power supply lines
108
a
and the branch ground lines
108
b
. This is because, under such a placement condition, the element power supply lines
106
a
of the cell rows
105
x
and the element ground lines
106
b
thereof are in contact with the branch power supply lines
108
a
and the branch ground lines
108
b
so that each of the element power supply lines
106
a
and the element ground lines
106
b
is short-circuited. In short, a portion of the cell placement region corresponding to the area occupied by the branch power supply lines
108
a
and the branch ground lines
108
b
is lost.
Thus, the conventional wiring structure is suitable for use in a semiconductor chip in which a fewer types of element circuits, such as a single digital circuit or a single SRAM (static random access memory), are integrated. In that case, the number of wiring layers is generally on the order of two. Since the number of wiring layers is small, an emphasis has been placed conventionally on the provision of an area for a region required for the signal lines.
However, the advent of a semiconductor chip having a plurality of circuits including a digital circuit, a SRAM, a DRAM (dynamic random access memory), a flash memory, and an analog circuit merged therein is expected in the future. Moreover, improvements in process technology allow miniaturization of elements in a semiconductor integrated circuit device so that an increase in the degree of integration of the digital circuit is also expected.
Therefore, the future trend in a semiconductor integrated circuit device is inevitably toward a larger wiring area required for the voltage supply lines of the individual element circuits and for signal l
McDermott Will & Emery LLP
Whitmore Stacy A.
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