Integrated circuit device and its manufacturing method

Details Integrated circuit device and its manufacturing method Integrated circuit device and its manufacturing method

2000-10-13

2003-10-28

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C438S627000

Reexamination Certificate

active

06639318

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an integrated circuit device having a Cu wiring and a method for producing the same.
BACKGROUND ART
There are requirements of refinement and high-speed response to integrated circuit devices. To satisfy such requirements, it is noted to use Cu, as material for wiring, which has a low resistance and a little electro-migration, instead of conventionally used Al. However, when Cu is used as the material for wiring, there is a problem of diffusion of Cu into a Si substrate or a dielectric layer. In order to prevent this problem, it is necessary to form a barrier layer between a Cu wiring layer and the Si substrate or the dielectric layer. The barrier layer is required to have high adhesive properties to Cu and the dielectric layer or the like as well as the capability of preventing the diffusion of Cu.
At present, Ti, TiN, Ta, TaN and WN are proposed as a barrier in a Cu wiring. In particular, Ta and TaN are noted by the reasons that they have a good barrier effect to Cu; they can easily be formed into a thin layer, and the adhesive properties to Cu, the dielectric layer and so on are excellent (U.S. Pat. No. 5,668,054).
Further, in a process for producing an integrated circuit device, a chemical-mechanical polishing (CMP) method is used to planarize each layer in order to form a large number of multilayer wiring. In CMP method for planarizing, however, Ta or TaN for a barrier layer has its nature of being hard mechanically and anti-corrosive to chemicals in comparison with Cu and the dielectric layer. Accordingly, it was difficult to process Cu and the dielectric layer together with the barrier layer by CMP method. If the processing was conducted to those simultaneously, there caused a phenomenon, called as dishing, that only Cu and the dielectric layer are recessed in a form of dish owing to the difference of characteristics of processing.
As a barrier layer different from the above-mentioned, Ti—Si—N series (JP-A-8-139092) and W—Si—N series (JP-A-9-64044) were proposed. However, they did not aim at improving the processing characteristics in using CMP method. Further, there was a proposal that TaON was provided in only a surface of the TaN barrier layer (JP-A-10-116831). However, this did not aim at improving the processing characteristics in using CMP method, and it was necessary to process the material, which is difficult to process, after TaON in the surface portion was removed.
DISCLOSURE OF THE INVENTION
The present invention is to provide an integrated circuit device having a Cu wiring layer, a barrier layer therefore and a dielectric layer, wherein the barrier layer is represented by a compositional formula of TaO
x
N
y
(the range of x being 0<x<2.5, and the range of y being 0<y<1).
Further, the present invention is to provide an integrated circuit device having a Cu wiring layer, a barrier layer therefore and a dielectric layer, wherein the barrier layer is represented by a compositional formula of Ta
1−a
M
a
O
b
N
c
(M being at least one member selected from the group consisting of elements of Groups 3, 4, 6, 7, 8, 9, 10, 12, 13 and 14 of the long form of the periodic table; the range of a being 0<a<1; the range of b being 0<b<2.5, and the range of c being 0<c<1).


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M. Stavrev, et al., Microelectronic Engineering, vol. 37-38, pps. 245-251, “Study of Ta(N,O) Diffusion Barrier Stability: Analytical and Electrical Characterization of Low Level Cu Contamination in Si,” Nov. 1, 1997.
M. Stavrev, et al., Thin Solid Films, vol. 307, No. 1-2, pps. 79-88, “Crystallographic and Morphological Characterization of Reactively Sputtered Ta, Ta-N and Ta-N and Ta-N-O Thin Films,” Oct. 10, 1997.
M. Stavrev, et al., Materials for Advanced Metallization, pps. 125-126, “Ultra Trace Analysis and Electrical Characterization of Cu Diffusion Through Thin Quasi-Amorphous Ta-N-O Barriers,” Mar. 16, 1997.
Stavrev et al. “Study of Ta(N,O) diffusion barrier stability: analytic and electrical characterization of low level Cu contamination in Si” Microelectronic Engineering Elsevier Publishers BV Amsterfam, NL, vol. 37-38 Nov. 1, 1997, pp. 245-251.

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